公开(公告)号：US11561912B2

公开(公告)日：2023-01-24

申请号：US17321916

申请日：2021-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungsub Shin ,  Sungho Seo ,  Kwanwoo Noh ,  Seongyong Jang ,  Haesung Jung

IPC: G06F13/16 ,  G06F13/18

Abstract: A host controller interface configured to provide interfacing between a host device and a storage device includes processing circuitry; a doorbell register configured to store a head pointer and a tail pointer of one or more first queues; and an entry buffer configured to store a first command from one of the one or more first queues in the entry buffer, wherein the processing circuitry is configured to, determine an order in which the commands of the one or more first queues are to be processed, route the first command to be stored in the entry buffer according to the determined order, and route a first response to be stored in one of one or more second queues.

公开(公告)号：US11914531B2

公开(公告)日：2024-02-27

申请号：US18064062

申请日：2022-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungsub Shin ,  Sungho Seo ,  Kwanwoo Noh ,  Seongyong Jang ,  Haesung Jung

IPC: G06F13/16 ,  G06F13/18

CPC classification number: G06F13/1673 ,  G06F13/18

Abstract: A host controller interface configured to provide interfacing between a host device and a storage device includes processing circuitry; a doorbell register configured to store a head pointer and a tail pointer of one or more first queues; and an entry buffer configured to store a first command from one of the one or more first queues in the entry buffer, wherein the processing circuitry is configured to, determine an order in which the commands of the one or more first queues are to be processed, route the first command to be stored in the entry buffer according to the determined order, and route a first response to be stored in one of one or more second queues.

公开(公告)号：US11809737B2

公开(公告)日：2023-11-07

申请号：US17238680

申请日：2021-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haesung Jung ,  Sungho Seo ,  Myungsub Shin ,  Seongyong Jang

IPC: G06F3/06 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F3/0655 ,  G06F3/061 ,  G06F3/0635 ,  G06F3/0679 ,  G06F13/385 ,  G06F13/4278

Abstract: Provided are a storage device configured to perform high-speed link startup and a storage system including the storage device. The storage system performs data communication through a connected transmission lane and a connected reception lane from among a plurality of lanes between a host and the storage device. The host transmits an activate period of the connected transmission lane, which is less than a first time period, to the connected reception lane, and the storage device receives the activate period of the connected reception lane, which is less than the first time period. The host and the storage device perform link startup in a high-speed mode through the connected transmission lane and the connected reception lane, based on the activate period being less than the first time period.

公开(公告)号：US11593031B2

公开(公告)日：2023-02-28

申请号：US17375328

申请日：2021-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungsub Shin ,  Sungho Seo ,  Seongyong Jang ,  Haesung Jung

IPC: G06F3/06

Abstract: An electronic device may include a host device and a storage device which are connected in a universal flash storage standard, wherein the host device may include processing circuitry configured to process a submission queue (SQ) and a completion queue (CQ), wherein the SQ is a processing standby line of a command, and the CQ is a processing standby line of a response received from the storage device, transmit the command to the storage device, store a host command credit in a host command register, the host command credit indicating an estimated command accommodation limit of the storage device, store the response in a response slot, and store a host response credit in a host command register, the host command credit indicating a limit of the response slot.