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    Semiconductor memory device and memory system including the same
    11.
    发明授权
    Semiconductor memory device and memory system including the same 有权

    公开(公告)号：US12236997B2

    公开(公告)日：2025-02-25

    申请号：US18357204

    申请日：2023-07-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung Kim ,  Taeyoung Oh ,  Jongcheol Kim ,  Kyungho Lee ,  Hyongryol Hwang

    IPC: G11C11/4078 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4096

    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a control logic circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data based on an active command applied to the control logic circuit at a first time point, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row in response to a precharge command applied at a second time point after a first command that is applied to the control logic circuit.

    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
    15.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20250028456A1

    公开(公告)日：2025-01-23

    申请号：US18907760

    申请日：2024-10-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyungho Lee ,  Kiheung Kim ,  Taeyoung Oh ,  Jongcheol Kim ,  Hyongryol Hwang

    IPC: G06F3/06

    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows and a row hammer management circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row. The row hammer management circuit includes a hammer address queue. The row hammer management circuit changes the updated count data randomly, based on an event signal indicating a state change of the hammer address queue.

    Semiconductor memory devices and memory systems including the same
    16.
    发明授权
    Semiconductor memory devices and memory systems including the same 有权

    公开(公告)号：US12118221B2

    公开(公告)日：2024-10-15

    申请号：US18136915

    申请日：2023-04-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongcheol Kim ,  Kiheung Kim ,  Taeyoung Oh ,  Kyungho Lee

    IPC: G06F12/00 ,  G06F3/06

    CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0679

    Abstract: A semiconductor memory device includes a memory cell array, a row hammer management circuit and a refresh control circuit. The row hammer management circuit automatically stores random count data in count cells of each of a plurality of memory cell rows during a power-up sequence of the semiconductor memory device and determines counted values by counting a number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller and stores the counted values in the count cells of each of the plurality of memory cell rows as count data. The refresh control circuit receives a hammer address and performs a hammer refresh operation on one or more of the plurality of memory cell rows that are physically adjacent to a memory cell row that corresponds to the hammer address.

    SEMICONDUCTOR MEMORY DEVICE
    17.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240220149A1

    公开(公告)日：2024-07-04

    申请号：US18243268

    申请日：2023-09-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung Kim ,  Taeyoung Oh

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0673

    Abstract: A semiconductor memory device includes a memory cell array and a column access circuit. The memory cell array includes a plurality of sub-array blocks and each of the sub-array blocks includes volatile memory cells. The column access circuit receives a plurality of data units, each of which includes normal data and meta data having a ratio of k:1, which is associated with managing the normal data, allocates p column selection lines associated with transferring the data units to the bit-lines to a plurality of normal data and a plurality of meta data in the data units with the ratio of k:1, and stores a sub unit of a first normal data among the plurality of normal data and a sub unit of a first meta data in a first region and a second region of a first sub-array block of the plurality of sub-array blocks, respectively.

    SEMICONDUCTOR MEMORY DEVICE AND METHODS OF OPERATION
    18.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND METHODS OF OPERATION 审中-公开

    公开(公告)号：US20230185460A1

    公开(公告)日：2023-06-15

    申请号：US18076628

    申请日：2022-12-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung Kim ,  Taeyoung Oh ,  Hyeran Kim ,  Sungyong Cho ,  Kyungsoo Ha

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673

    Abstract: A semiconductor memory device includes a memory cell array, a row hammer management circuit and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The row hammer management circuit counts the number of instances of access of each of the memory cell rows, such as in response to the receipt of an active command, to store the counted values in count cells of each of the memory cell rows as count data and, in response to a first command, initiates an internal read-update-write operation to read the count data, to update the read count data, and to write the updated count data in the count cells. The control logic circuit may performs an internal write operation to write the updated count data in the count cells during a second write time interval that is smaller than a first write time interval associated with a normal write operation.

    Semiconductor memory devices and methods of operating semiconductor memory devices
    19.
    发明授权
    Semiconductor memory devices and methods of operating semiconductor memory devices 有权

    公开(公告)号：US11487615B2

    公开(公告)日：2022-11-01

    申请号：US17205276

    申请日：2021-03-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung Kim ,  Hyungi Kim ,  Junhyung Kim ,  Sungchul Park ,  Yesin Ryu

    IPC: G06F11/10 ,  G11C11/4096 ,  G11C11/406 ,  G11C11/408 ,  H01L25/065

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a scrubbing control circuit and a control logic circuit. The memory cell array includes memory cell rows, and each of the memory cell rows including volatile memory cells. The scrubbing control circuit generates scrubbing addresses for performing a normal scrubbing operation on the memory cell rows with a first period based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC engine the scrubbing control circuit to distribute a scrubbing operation on weak codewords dynamically within the refresh operation such that a dynamic allocated scrubbing (DAS) operation is performed with a second period smaller than the first period. An error bit is detected in each of the weak codewords during the normal scrubbing operation or normal read operation on at least one of the memory cell rows.

    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES
    20.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20220093200A1

    公开(公告)日：2022-03-24

    申请号：US17245075

    申请日：2021-04-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung Kim ,  Sanguhn Cha ,  Junhyung Kim ,  Sungchul Park ,  Hyojin Jung ,  Kyung-Soo Ha

    IPC: G11C29/42 ,  G11C29/44 ,  G11C29/20 ,  G11C11/406

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register, a scrubbing control circuit and a control logic circuit. The memory cell array includes memory cell rows. The scrubbing control circuit generates scrubbing addresses based on refresh operations performed on the memory cell array. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection operation on a plurality of sub-pages in a first memory cell row to count a number of error occurrences, and determines whether to correct a codeword in which an error is detected based on the number of error occurrences. An uncorrected or corrected codeword is written back , and a row address of the first memory cell row may be stored in the fault address register as a row fault address based on the number of error occurrences.

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