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    MEMORY DEVICES HAVING VARIABLE REPAIR UNITS THEREIN AND METHODS OF REPAIRING SAME
    4.
    发明申请
    MEMORY DEVICES HAVING VARIABLE REPAIR UNITS THEREIN AND METHODS OF REPAIRING SAME 有权

    公开(公告)号：US20230069753A1

    公开(公告)日：2023-03-02

    申请号：US18053498

    申请日：2022-11-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yesin Ryu ,  Yoonna Oh ,  Hyunki Kim

    IPC: G11C29/00 ,  G06F11/20 ,  G06F12/10 ,  G11C17/16 ,  G11C17/18

    Abstract: A memory device includes a row decoder, a column decoder, and a repair control circuit, which is configured to: (i) compare a row address with a stored failed row address, (ii) compare a column address with a stored failed column address, (iii) control the row decoder to activate the at least one of a plurality of redundancy word lines when the row address corresponds to the failed row address, and (iv) control the column decoder to activate at least one of a plurality of redundancy bit lines when the column address corresponds to the failed column address. The repair control circuit varies a repair unit according to an address input during a repair operation.

    Semiconductor memory devices and methods of operating semiconductor memory devices
    5.
    发明授权
    Semiconductor memory devices and methods of operating semiconductor memory devices 有权

    公开(公告)号：US11487615B2

    公开(公告)日：2022-11-01

    申请号：US17205276

    申请日：2021-03-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung Kim ,  Hyungi Kim ,  Junhyung Kim ,  Sungchul Park ,  Yesin Ryu

    IPC: G06F11/10 ,  G11C11/4096 ,  G11C11/406 ,  G11C11/408 ,  H01L25/065

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a scrubbing control circuit and a control logic circuit. The memory cell array includes memory cell rows, and each of the memory cell rows including volatile memory cells. The scrubbing control circuit generates scrubbing addresses for performing a normal scrubbing operation on the memory cell rows with a first period based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC engine the scrubbing control circuit to distribute a scrubbing operation on weak codewords dynamically within the refresh operation such that a dynamic allocated scrubbing (DAS) operation is performed with a second period smaller than the first period. An error bit is detected in each of the weak codewords during the normal scrubbing operation or normal read operation on at least one of the memory cell rows.

    Semiconductor memory devices
    6.
    发明授权
    Semiconductor memory devices 有权

    公开(公告)号：US11366716B2

    公开(公告)日：2022-06-21

    申请号：US17088900

    申请日：2020-11-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yesin Ryu ,  Namsung Kim ,  Sanguhn Cha ,  Jaeyoun Youn ,  Kijun Lee

    IPC: G06F11/10 ,  H01L25/065

    Abstract: A semiconductor memory device including: a buffer die; memory dies stacked on the buffer die; and TSVs, at least one of the memory dies includes: a memory cell array; an error correction code (ECC) engine; an error information register; and a control logic circuit configured to control the ECC engine to perform a read-modify-write operation, wherein the control logic circuit is configured to: record, in the error information register, a first address associated with a first codeword based on the an generation signal and a first syndrome obtained by an ECC decoding; and determine an error attribute of the first codeword based on a change of the first syndrome, recorded in the error information register, based on a plurality of read-modify-write operations.

    Semiconductor memory devices and memory systems
    7.
    发明授权
    Semiconductor memory devices and memory systems 有权

    公开(公告)号：US11170868B2

    公开(公告)日：2021-11-09

    申请号：US16864787

    申请日：2020-05-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yesin Ryu ,  Sanguhn Cha ,  Sunghye Cho ,  Kijun Lee ,  Myungkyu Lee ,  Youngcheon Kwon ,  Jaeyoun Youn

    IPC: G11C29/00 ,  G11C29/42 ,  G11C29/14 ,  G11C7/10 ,  G11C29/44 ,  G11C29/12

    Abstract: A semiconductor memory device includes a memory cell array and an interface circuit including an error correction code (ECC) engine. The memory cell array includes a plurality of volatile memory cells, a normal cell region and a parity cell region. The interface circuit, in a write operation, receives main data and first parity data from an external device, the first parity data being generated based on a first ECC and stores the main data in the normal cell region and the first parity data in the parity cell region. The interface circuit, in a read operation, performs an ECC decoding on the main data using a second ECC, based on the first parity data to correct a first type of error in the main data. The second ECC has a parity check matrix which is the same as a parity check matrix of the first ECC.

    MEMORY DEVICES HAVING VARIABLE REPAIR UNITS THEREIN AND METHODS OF REPAIRING SAME
    8.
    发明申请
    MEMORY DEVICES HAVING VARIABLE REPAIR UNITS THEREIN AND METHODS OF REPAIRING SAME 有权

    公开(公告)号：US20210124659A1

    公开(公告)日：2021-04-29

    申请号：US16890559

    申请日：2020-06-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yesin Ryu ,  Yoonna Oh ,  Hyunki Kim

    IPC: G06F11/20 ,  G06F12/10 ,  G11C29/00 ,  G11C17/16 ,  G11C17/18

    Abstract: A memory device includes a row decoder, a column decoder, and a repair control circuit, which is configured to: (i) compare a row address with a stored failed row address, (ii) compare a column address with a stored failed column address, (iii) control the row decoder to activate the at least one of a plurality of redundancy word lines when the row address corresponds to the failed row address, and (iv) control the column decoder to activate at least one of a plurality of redundancy bit lines when the column address corresponds to the failed column address. The repair control circuit varies a repair unit according to an address input during a repair operation.

    Semiconductor memory devices and memory systems including the same
    10.
    发明授权
    Semiconductor memory devices and memory systems including the same 有权

    公开(公告)号：US11551775B2

    公开(公告)日：2023-01-10

    申请号：US17313236

    申请日：2021-05-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sunggi Ahn ,  Yesin Ryu ,  Jun Jin Kong ,  Eunae Lee ,  Jihyun Choi

    IPC: G11C29/14 ,  G11C29/42 ,  G11C29/46 ,  G11C29/52 ,  G11C29/12

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit and a control logic circuit to control the ECC circuit. The memory cell array includes memory cells and a normal cell region and a parity cell region The ECC circuit, in a normal mode, receives a main data, performs an ECC encoding on the main data to generate a parity data and stores the main data and the parity data in the normal cell region and the parity cell region. The ECC circuit, in a test mode, receives a test data including at least one error bit, stores the test data in one of the normal cell region and the parity cell region and performs an ECC decoding on the test data and one of the main data and the parity data to provide a decoding result data to an external device.

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