公开(公告)号：US20240071923A1

公开(公告)日：2024-02-29

申请号：US18209820

申请日：2023-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjun SONG ,  Jongmin LEE ,  Joongwon SHIN ,  Nara LEE ,  Jimin CHOI

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/53295 ,  H01L24/16 ,  H01L25/0657 ,  H10B80/00 ,  H01L23/53228 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A semiconductor device may include lower metal wirings on a substrate, a first upper insulating interlayer on the lower metal wirings, a first upper wiring including a first upper via in the first upper insulating interlayer and a first upper metal pattern on the first upper insulating interlayer. The semiconductor device may also include a second upper insulating interlayer on the first upper insulating interlayer, an uppermost wiring including an uppermost via in the second upper insulating interlayer, an uppermost metal pattern on the second upper insulating interlayer, and an oxide layer for supplying hydrogen on the second upper insulating interlayer. The lower metal wirings may be stacked in a plurality of layers. The oxide layer for supplying hydrogen may cover the uppermost wiring. A thickness of the uppermost via may be less than 40% of a thickness of the uppermost metal pattern.

公开(公告)号：US20230043650A1

公开(公告)日：2023-02-09

申请号：US17964244

申请日：2022-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon CHANG ,  Jimin CHOI ,  Yeonjin LEE ,  Hyeon-Woo JANG ,  Jung-Hoon HAN

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

公开(公告)号：US20230030117A1

公开(公告)日：2023-02-02

申请号：US17714202

申请日：2022-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juik LEE ,  Jong-Min LEE ,  Jimin CHOI ,  Yeonjin LEE ,  Jeon Il LEE

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H01L23/00 ,  H01L25/10

Abstract: A semiconductor device includes a substrate including a first side and a second side opposite to each other, a first penetrating structure that penetrates the substrate, and a second penetrating structure that penetrates the substrate, the second penetrating structure being spaced apart from the first penetrating structure, and an area of the first penetrating structure being more than twice an area of the second penetrating structure, as viewed from the first side of the substrate.

公开(公告)号：US20210305153A1

公开(公告)日：2021-09-30

申请号：US17153963

申请日：2021-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon CHANG ,  Jimin CHOI ,  Yeonjin LEE ,  Hyeon-Woo JANG ,  Jung-Hoon HAN

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

公开(公告)号：US20210020495A1

公开(公告)日：2021-01-21

申请号：US17039431

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Dong LEE ,  KEUNNAM KIM ,  Dongryul LEE ,  Minseong CHOI ,  Jimin CHOI ,  YONG KWAN KIM ,  CHANGHYUN CHO ,  YOOSANG HWANG

IPC: H01L21/768 ,  H01L27/108 ,  H01L23/532 ,  H01L23/535

Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.

公开(公告)号：US20250062193A1

公开(公告)日：2025-02-20

申请号：US18934456

申请日：2024-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonil LEE ,  Jongmin LEE ,  Jimin CHOI ,  Yeonjin LEE

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535

Abstract: A semiconductor device includes a substrate including a first surface, and a second surface opposing the first surface. A via insulating layer extending through the substrate is disposed. A through-silicon via extending through the via insulating layer is disposed. The center of the through-silicon via is misaligned from the center of the via insulating layer. A blocking layer is disposed on the first surface. A first insulating layer is disposed on the blocking layer. A contact plug contacting the through-silicon via and extending through the first insulating layer and the blocking layer is disposed.

公开(公告)号：US20240153919A1

公开(公告)日：2024-05-09

申请号：US18451197

申请日：2023-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong KIM ,  Jongmin LEE ,  Jimin CHOI

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3142 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/08113 ,  H01L2224/0903 ,  H01L2224/16148 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A semiconductor package includes a first semiconductor chip including a circuit layer on a first substrate, first through silicon vias passing through the first substrate, first lower bump pads on the circuit layer, and a first upper bump pad and a second upper bump pad on a second surface of the first substrate, each of the first upper bump pad and the second upper bump pad connected to a corresponding one of the first through silicon vias. The package includes a second semiconductor chip including a circuit layer on a first surface of a second substrate, and second lower bump pads on the circuit layer on the second substrate. The package includes a first solder bump to bond the first upper bump pad and the second lower bump pad, and a plurality of second solder bumps to bond the second upper bump pad and the second lower bump pads.

公开(公告)号：US20240038675A1

公开(公告)日：2024-02-01

申请号：US18313491

申请日：2023-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jimin CHOI ,  Joongwon SHIN ,  Sungyun WOO ,  Yeonjin LEE ,  Jongmin LEE ,  Sehyun HWANG

IPC: H01L23/544 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/544 ,  H01L25/0657 ,  H01L25/18 ,  H10B80/00 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2225/06593 ,  H01L2223/54426

Abstract: A semiconductor device may include a plurality of chip regions on a substrate, at least one scribe lane surrounding each of the plurality of chip regions on the substrate, a plurality of first align key patterns and a plurality of first test element group patterns included in the plurality of chip regions, and a plurality of second align key patterns and a plurality of second test element group patterns included in the at least one scribe lane.

公开(公告)号：US20230116911A1

公开(公告)日：2023-04-13

申请号：US17736212

申请日：2022-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonil LEE ,  Jongmin LEE ,  Jimin CHOI ,  Yeonjin LEE

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/535 ,  H01L21/768

Abstract: A semiconductor device includes a substrate including a first surface, and a second surface opposing the first surface. A via insulating layer extending through the substrate is disposed. A through-silicon via extending through the via insulating layer is disposed. The center of the through-silicon via is misaligned from the center of the via insulating layer. A blocking layer is disposed on the first surface. A first insulating layer is disposed on the blocking layer. A contact plug contacting the through-silicon via and extending through the first insulating layer and the blocking layer is disposed.

公开(公告)号：US20230077803A1

公开(公告)日：2023-03-16

申请号：US17751740

申请日：2022-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jimin CHOI ,  Jongmin LEE ,  Yeonjin LEE ,  Jeonil LEE ,  Juik LEE ,  Minjung CHOI

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor device includes a substrate, an etch stop layer on the substrate, a through-hole electrode extending through the substrate and the etch stop layer in a vertical direction substantially perpendicular to an upper surface of the substrate, and a conductive pad. The etch stop layer includes a first surface adjacent to the substrate and a second surface opposite the first surface. The through-hole electrode includes a protrusion portion that protrudes from the second surface of the etch stop layer. The conductive pad covers the protrusion portion of the through-hole electrode. The protrusion portion of the through-hole electrode is not flat.