公开(公告)号：US20180210421A1

公开(公告)日：2018-07-26

申请号：US15867939

申请日：2018-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WOOTAE KIM ,  Hyung-Ock Kim ,  Jaehoon Kim ,  Naya Ha ,  Ki-Ok Kim ,  Eunbyeol Kim ,  Jung Yun Choi ,  Sun Ik Heo

IPC: G05B19/4097 ,  G06F17/50

CPC classification number: G05B19/4097 ,  G05B2219/45031 ,  G06F17/5072 ,  G06F2217/12 ,  Y02P90/265

Abstract: A method of manufacturing an integrated circuit (IC) including instances of standard cells includes arranging a first instance and arranging a second instance adjacent to the first instance. The second instance has a front-end layer pattern corresponding to a context group of the first instance. The context group includes information about front-end layer patterns of instances, the front-end layer patterns causing a same local layout effect (LLE) on the first instance and arranged adjacent to the first instance.

公开(公告)号：US12239026B2

公开(公告)日：2025-02-25

申请号：US17748127

申请日：2022-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehoon Kim

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: An embedded device includes a substrate including a magnetic random access memory (MRAM) region, the MRAM region having a cell block region, magnetic tunnel junction (MTJ) modules in the cell block region, each of the MTJ modules including a MTJ pattern, an insulating interlayer structure covering the MTJ modules, and magnetic field shielding structures in the insulating interlayer structure and adjacent to an outside of the cell block region, each of the magnetic field shielding structures extending in a vertical direction to face at least from an upper end of the MTJ pattern to a lower end of the MTJ pattern, and each of the magnetic field shielding structures including a ferromagnetic material.

公开(公告)号：US20240319761A1

公开(公告)日：2024-09-26

申请号：US18609073

申请日：2024-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeyoung Lee ,  Byungsu Kim ,  Youngsan Kim ,  Jaegon Lee ,  Jaehoon Kim ,  Byeongho Lee ,  Jongjin Lee ,  Wookyeong Jeong

IPC: G06F1/08 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H03K5/133 ,  H03K5/1534

CPC classification number: G06F1/08 ,  H03K5/133 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16225 ,  H03K5/1534

Abstract: A semiconductor device includes an intellectual property (IP) block configured to operate based on a first clock signal and a power voltage, a clock gating circuit configured to operate based on the power voltage, and generate the first clock signal by selectively performing clock gating on a second clock signal based on an enable signal, and a critical path monitor (CPM) configured to generate a digital code having a value, which varies according to a voltage drop of the power voltage, and activate the enable signal based on a comparison of the value of the digital code with a reference value.

公开(公告)号：US12029134B2

公开(公告)日：2024-07-02

申请号：US17402960

申请日：2021-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghwan Park ,  Younghyun Kim ,  Jaehoon Kim ,  Heeju Shin ,  Sechung Oh

IPC: H10N50/85 ,  H01L23/522 ,  H01L23/528 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80

CPC classification number: H10N50/10 ,  H01L23/5226 ,  H01L23/5283 ,  H10B61/22 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor device including a substrate; a lower electrode on the substrate; a magnetic tunnel junction structure on the lower electrode, the magnetic tunnel junction structure including a pinned layer, a tunnel barrier layer, and a free layer which are sequentially stacked; an upper electrode on the magnetic tunnel junction structure; and an oxidation control layer between the free layer and the upper electrode, the oxidation control layer including at least one filter layer and at least one oxide layer, wherein the at least one filter layer includes MoCoFe.

公开(公告)号：US11700723B2

公开(公告)日：2023-07-11

申请号：US17193739

申请日：2021-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjae Jung ,  Kwangho Park ,  Jaehoon Kim

IPC: H01L27/06 ,  H10B12/00

CPC classification number: H10B12/30 ,  H10B12/03 ,  H10B12/05

Abstract: A semiconductor memory device, including a first semiconductor pattern, and a second semiconductor pattern separated from the first semiconductor pattern in a vertical direction; a first bit line electrically connected to a first source/drain region of the first semiconductor pattern, and a second bit line electrically connected to a first source/drain region of the second semiconductor pattern; a word line structure in contact with the first semiconductor pattern and the second semiconductor pattern; and a first data storage element electrically connected to a second source/drain region of the first semiconductor pattern, and a second data storage element electrically connected to a second source/drain region of the second semiconductor pattern, wherein the first semiconductor pattern and the second semiconductor pattern are monocrystalline, and wherein a crystal orientation of the first semiconductor pattern is different from a crystal orientation of the second semiconductor pattern.

公开(公告)号：US11437382B2

公开(公告)日：2022-09-06

申请号：US16916366

申请日：2020-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunji Song ,  Jaehoon Kim ,  Kwangho Park ,  Yonghoon Son ,  Gyeonghee Lee ,  Seungjae Jung

IPC: H01L27/108

Abstract: An integrated circuit device includes a plurality of semiconductor layers stacked on a substrate to overlap each other in a vertical direction and longitudinally extending along a first horizontal direction. The plurality of semiconductor layers may have different thicknesses in the vertical direction.

公开(公告)号：US10599130B2

公开(公告)日：2020-03-24

申请号：US15867939

申请日：2018-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wootae Kim ,  Hyung-Ock Kim ,  Jaehoon Kim ,  Naya Ha ,  Ki-Ok Kim ,  Eunbyeol Kim ,  Jung Yun Choi ,  Sun Ik Heo

IPC: G06F17/50 ,  G05B19/4097

Abstract: A method of manufacturing an integrated circuit (IC) including instances of standard cells includes arranging a first instance and arranging a second instance adjacent to the first instance. The second instance has a front-end layer pattern corresponding to a context group of the first instance. The context group includes information about front-end layer patterns of instances, the front-end layer patterns causing a same local layout effect (LLE) on the first instance and arranged adjacent to the first instance.

公开(公告)号：US12190928B2

公开(公告)日：2025-01-07

申请号：US17970788

申请日：2022-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younghyun Kim ,  Sechung Oh ,  Heeju Shin ,  Jaehoon Kim ,  Sanghwan Park ,  Junghwan Park

IPC: G11C11/00 ,  G11C11/16 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetoresistive random access memory device includes a pinned layer; a tunnel barrier layer on the pinned layer; a free layer structure on the tunnel barrier layer, the free layer structure including a plurality of magnetic layers and a plurality of metal insertion layers between the magnetic layers; and an upper oxide layer on the free layer structure, wherein each of the metal insertion layers includes a non-magnetic metal material doped with a magnetic material, and the metal insertion layers are spaced apart from each other.

公开(公告)号：US11966288B2

公开(公告)日：2024-04-23

申请号：US17668813

申请日：2022-02-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehoon Kim ,  Sungjun Kim ,  Kyuseon Son ,  Seunghee Shin ,  Myunggyun Yoon ,  Youngchang Lee

IPC: G06F11/10 ,  G06F11/263 ,  G06F11/27 ,  G06F11/32

CPC classification number: G06F11/1068 ,  G06F11/263 ,  G06F11/27 ,  G06F11/327

Abstract: In an electronic apparatus, a processor executes a program stored in memory to perform essential functions. In the event of an error related to these functions, a self-test application is triggered. The processor may identify a relevant test routine from a set of routines, conduct tests on the function using the identified routine, and communicate the test results to a display. Accordingly, when an error occurs while the electronic apparatus is operating, the electronic apparatus can inform a user and a manufacturer of a cause of the error.

公开(公告)号：US11623525B2

公开(公告)日：2023-04-11

申请号：US16728406

申请日：2019-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngseok Lee ,  Taewon Um ,  Jaehoon Kim ,  Hyewon Kim ,  Seungwoo Shin ,  Yuhyeon Jun ,  Yongjin Choi ,  Wooseok Hwang

IPC: B60K37/06 ,  B60K35/00 ,  B60K37/02

Abstract: An electronic apparatus disposed in a vehicle is provided. The electronic apparatus includes an input device including a body configured to be rotatable and pushable and a display disposed on the body; and a processor configured to acquire profile data of a user including preset information for function of the vehicle, control the display to display basic user interface (UI) corresponding to the function of the vehicle based on the acquired profile data of the user, and control a function of the vehicle corresponding to the basic UI in response to receiving an input on the input device.