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公开(公告)号：US20240192752A1
公开(公告)日：2024-06-13
申请号：US18584309
申请日：2024-02-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaegon LEE , Yohan Kwon , Sangho Kim , Seki Kim , Joonseok Kim , Yooseok Shon , Dooseok Yoon , Iksu Lee , Jongpil Lee , Hyongmin Lee , Wookyeong Jeong
Abstract: A system on chip includes a core configured to maintain a clock gating state; a plurality of header switch circuits configured to deliver a supply voltage, which is reduced from an external supply voltage, to the core in response to a plurality of control signals; and a voltage regulator configured to monitor the supply voltage, change logic levels of the plurality of control signals according to a difference level corresponding to a difference between the supply voltage and a preset target voltage, and output the plurality of control signals of which the logic levels have been changed to the plurality of header switch circuits.
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公开(公告)号：US20240319761A1
公开(公告)日：2024-09-26
申请号：US18609073
申请日：2024-03-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaeyoung Lee , Byungsu Kim , Youngsan Kim , Jaegon Lee , Jaehoon Kim , Byeongho Lee , Jongjin Lee , Wookyeong Jeong
IPC: G06F1/08 , H01L23/00 , H01L23/498 , H01L25/10 , H03K5/133 , H03K5/1534
CPC classification number: G06F1/08 , H03K5/133 , H01L23/49816 , H01L24/16 , H01L25/105 , H01L2224/16225 , H03K5/1534
Abstract: A semiconductor device includes an intellectual property (IP) block configured to operate based on a first clock signal and a power voltage, a clock gating circuit configured to operate based on the power voltage, and generate the first clock signal by selectively performing clock gating on a second clock signal based on an enable signal, and a critical path monitor (CPM) configured to generate a digital code having a value, which varies according to a voltage drop of the power voltage, and activate the enable signal based on a comparison of the value of the digital code with a reference value.
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公开(公告)号：US11947401B2
公开(公告)日：2024-04-02
申请号：US17559684
申请日：2021-12-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaegon Lee , Yohan Kwon , Sangho Kim , Seki Kim , Joonseok Kim , Yooseok Shon , Dooseok Yoon , Iksu Lee , Jongpil Lee , Hyongmin Lee , Wookyeong Jeong
Abstract: A system on chip includes a core configured to maintain a clock gating state; a plurality of header switch circuits configured to deliver a supply voltage, which is reduced from an external supply voltage, to the core in response to a plurality of control signals; and a voltage regulator configured to monitor the supply voltage, change logic levels of the plurality of control signals according to a difference level corresponding to a difference between the supply voltage and a preset target voltage, and output the plurality of control signals of which the logic levels have been changed to the plurality of header switch circuits.
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公开(公告)号：US20220253117A1
公开(公告)日：2022-08-11
申请号：US17559684
申请日：2021-12-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaegon Lee , Yohan Kwon , Sangho Kim , Seki Kim , Joonseok Kim , Yooseok Shon , Dooseok Yoon , Iksu Lee , Jongpil Lee , Hyongmin Lee , Wookyeong Jeong
Abstract: A system on chip includes a core configured to maintain a clock gating state; a plurality of header switch circuits configured to deliver a supply voltage, which is reduced from an external supply voltage, to the core in response to a plurality of control signals; and a voltage regulator configured to monitor the supply voltage, change logic levels of the plurality of control signals according to a difference level corresponding to a difference between the supply voltage and a preset target voltage, and output the plurality of control signals of which the logic levels have been changed to the plurality of header switch circuits.
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