公开(公告)号：US20240192752A1

公开(公告)日：2024-06-13

申请号：US18584309

申请日：2024-02-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaegon LEE ,  Yohan Kwon ,  Sangho Kim ,  Seki Kim ,  Joonseok Kim ,  Yooseok Shon ,  Dooseok Yoon ,  Iksu Lee ,  Jongpil Lee ,  Hyongmin Lee ,  Wookyeong Jeong

IPC: G06F1/28 ,  G05F1/59 ,  H02M3/157

CPC classification number: G06F1/28 ,  G05F1/59 ,  H02M3/157

Abstract: A system on chip includes a core configured to maintain a clock gating state; a plurality of header switch circuits configured to deliver a supply voltage, which is reduced from an external supply voltage, to the core in response to a plurality of control signals; and a voltage regulator configured to monitor the supply voltage, change logic levels of the plurality of control signals according to a difference level corresponding to a difference between the supply voltage and a preset target voltage, and output the plurality of control signals of which the logic levels have been changed to the plurality of header switch circuits.

公开(公告)号：US20210116955A1

公开(公告)日：2021-04-22

申请号：US15931043

申请日：2020-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byung-Su Kim ,  Taekkyun Shin ,  Chun-Guan Kim ,  Yohan Kwon ,  Yun Heo

IPC: G06F1/08 ,  G06F1/26 ,  G06F11/30 ,  G06F9/54

Abstract: A dynamic power monitor for monitoring a power of a block in an integrated circuit is provided. The dynamic power monitor includes an input buffer configured to store first state values corresponding to internal signals of the block according to a first cycle of a clock signal; a power calculator configured to identify first power classification values corresponding to the block according to the first cycle, based on the first state values; and a filter configured to identify a first filtered value of the first power classification values.

公开(公告)号：US11947401B2

公开(公告)日：2024-04-02

申请号：US17559684

申请日：2021-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaegon Lee ,  Yohan Kwon ,  Sangho Kim ,  Seki Kim ,  Joonseok Kim ,  Yooseok Shon ,  Dooseok Yoon ,  Iksu Lee ,  Jongpil Lee ,  Hyongmin Lee ,  Wookyeong Jeong

IPC: G06F1/28 ,  G05F1/59 ,  H02M3/157

CPC classification number: G06F1/28 ,  G05F1/59 ,  H02M3/157

Abstract: A system on chip includes a core configured to maintain a clock gating state; a plurality of header switch circuits configured to deliver a supply voltage, which is reduced from an external supply voltage, to the core in response to a plurality of control signals; and a voltage regulator configured to monitor the supply voltage, change logic levels of the plurality of control signals according to a difference level corresponding to a difference between the supply voltage and a preset target voltage, and output the plurality of control signals of which the logic levels have been changed to the plurality of header switch circuits.

公开(公告)号：US11442491B2

公开(公告)日：2022-09-13

申请号：US15931043

申请日：2020-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byung-Su Kim ,  Taekkyun Shin ,  Chun-Guan Kim ,  Yohan Kwon ,  Yun Heo

IPC: G06F1/08 ,  G06F1/26 ,  G06F9/54 ,  G06F11/30 ,  G06F1/10 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3296 ,  G06F1/3206 ,  G06F1/06 ,  G06F1/3237

Abstract: A dynamic power monitor for monitoring a power of a block in an integrated circuit is provided. The dynamic power monitor includes an input buffer configured to store first state values corresponding to internal signals of the block according to a first cycle of a clock signal; a power calculator configured to identify first power classification values corresponding to the block according to the first cycle, based on the first state values; and a filter configured to identify a first filtered value of the first power classification values.

公开(公告)号：US20220253117A1

公开(公告)日：2022-08-11

申请号：US17559684

申请日：2021-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaegon Lee ,  Yohan Kwon ,  Sangho Kim ,  Seki Kim ,  Joonseok Kim ,  Yooseok Shon ,  Dooseok Yoon ,  Iksu Lee ,  Jongpil Lee ,  Hyongmin Lee ,  Wookyeong Jeong

IPC: G06F1/28 ,  H02M3/157

Abstract: A system on chip includes a core configured to maintain a clock gating state; a plurality of header switch circuits configured to deliver a supply voltage, which is reduced from an external supply voltage, to the core in response to a plurality of control signals; and a voltage regulator configured to monitor the supply voltage, change logic levels of the plurality of control signals according to a difference level corresponding to a difference between the supply voltage and a preset target voltage, and output the plurality of control signals of which the logic levels have been changed to the plurality of header switch circuits.