DISPLAY PANEL, MANUFACTURING METHOD OF THE SAME, AND ELECTRONIC DEVICE

    公开(公告)号:US20250142967A1

    公开(公告)日:2025-05-01

    申请号:US18914400

    申请日:2024-10-14

    Abstract: A display panel includes a substrate, a gate electrode disposed on the substrate, a two-dimensional semiconductor material layer overlapping the gate electrode, a source electrode and a drain electrode electrically connected to the two-dimensional semiconductor material layer, a first electrode of a micro light-emitting diode electrically connected to the drain electrode, an active layer electrically connected to the first electrode of the micro light-emitting diode, where the active layer includes a quantum well layer surrounded by an ion-doped insulating partition, and a second electrode of the micro light-emitting diode electrically connected to the active layer.

    Imaging device and electronic device including the same

    公开(公告)号:US11611695B2

    公开(公告)日:2023-03-21

    申请号:US17038577

    申请日:2020-09-30

    Abstract: An imaging device includes a light source operating in response to an optical control signal having a predetermined frequency, a sensor including a plurality of pixels, configured to generate an electrical signal in response to a light reception signal output by the light source and reflected from a subject, and a logic circuit configured to generate first raw data of a spatial domain based on the electrical signal, and an image signal processor configured to convert the first raw data into second raw data of a frequency domain, to select low-frequency data of the second raw data within a frequency band lower than a predetermined reference frequency, to apply a predetermined weighting to the low-frequency data to generate weighted data, and to generate a resultant image based on the first raw data and the weighted data.

    SYSTEM ON CHIP
    8.
    发明申请

    公开(公告)号:US20220253117A1

    公开(公告)日:2022-08-11

    申请号:US17559684

    申请日:2021-12-22

    Abstract: A system on chip includes a core configured to maintain a clock gating state; a plurality of header switch circuits configured to deliver a supply voltage, which is reduced from an external supply voltage, to the core in response to a plurality of control signals; and a voltage regulator configured to monitor the supply voltage, change logic levels of the plurality of control signals according to a difference level corresponding to a difference between the supply voltage and a preset target voltage, and output the plurality of control signals of which the logic levels have been changed to the plurality of header switch circuits.

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