公开(公告)号：US20220293514A1

公开(公告)日：2022-09-15

申请号：US17669049

申请日：2022-02-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongwee YU ,  Iksu LEE ,  Jaegon LEE

IPC: H01L23/522 ,  H01L23/50 ,  H01L23/64 ,  H01L49/02 ,  G06F1/26

Abstract: A system on chip includes a processing unit including the first processing circuit and a second processing circuit, a connection circuit configured to form a path connecting one of the first processing circuit and the second processing circuit to an external capacitor, and a controller configured to control the connection circuit based on a state of at least one of the first processing circuit and the second processing circuit.

公开(公告)号：US20240192752A1

公开(公告)日：2024-06-13

申请号：US18584309

申请日：2024-02-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaegon LEE ,  Yohan Kwon ,  Sangho Kim ,  Seki Kim ,  Joonseok Kim ,  Yooseok Shon ,  Dooseok Yoon ,  Iksu Lee ,  Jongpil Lee ,  Hyongmin Lee ,  Wookyeong Jeong

IPC: G06F1/28 ,  G05F1/59 ,  H02M3/157

CPC classification number: G06F1/28 ,  G05F1/59 ,  H02M3/157

Abstract: A system on chip includes a core configured to maintain a clock gating state; a plurality of header switch circuits configured to deliver a supply voltage, which is reduced from an external supply voltage, to the core in response to a plurality of control signals; and a voltage regulator configured to monitor the supply voltage, change logic levels of the plurality of control signals according to a difference level corresponding to a difference between the supply voltage and a preset target voltage, and output the plurality of control signals of which the logic levels have been changed to the plurality of header switch circuits.

公开(公告)号：US20140068331A1

公开(公告)日：2014-03-06

申请号：US14047304

申请日：2013-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsun AHN ,  Jaegon LEE

IPC: G06F11/273

CPC classification number: G06F11/2733 ,  G01R31/31705 ,  G01R31/318572

Abstract: A test system for debugging a target device includes a switch unit configured to transfer a test signal to the target device, the target device including a first intellectual property (IP) block supporting a debugging operation at a normal mode and a second IP block supporting a debugging operation at a power saving mode. The switch unit is configured to form a first signal transfer path for transferring the test signal to the first IP block at the normal mode and to form a second signal transfer path for transferring the test signal to the second IP block at the power saving mode.

Abstract translation: 用于调试目标设备的测试系统包括被配置为将测试信号传送到目标设备的开关单元，所述目标设备包括支持正常模式下的调试操作的第一知识产权（IP）块和支持正常模式的第二IP块 在省电模式下进行调试操作。 开关单元被配置为形成用于在正常模式下将测试信号传送到第一IP块的第一信号传送路径，并且形成用于在功率节省模式下将测试信号传送到第二IP块的第二信号传送路径。