公开(公告)号：US11482278B2

公开(公告)日：2022-10-25

申请号：US17369010

申请日：2021-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pavan Kumar Kasibhatla ,  Seong-il O ,  Hak-soo Yu

IPC: G11C11/4091 ,  G11C11/408 ,  G06F15/78 ,  G11C11/4096 ,  G11C7/10 ,  G11C11/4093

Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

公开(公告)号：US20220076717A1

公开(公告)日：2022-03-10

申请号：US17124056

申请日：2020-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eldho Pathiyakkara Thombra Mathew ,  Anirudh Birur Kiran ,  Hak-soo Yu ,  Praful Ramesh Orakkan

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/20

Abstract: A memory system includes a memory device including memory banks and a data bus management circuit and a host coupled to the memory device. The host includes a memory controller detecting at least one trigger initiated by at least one application for performing at least one operation on data stored within the memory device, the at least one operation including at least one of a data copy operation, and a data processing operation, and performing the at least one operation on the data within the memory device by enabling movement of the data between the data bus management circuit of the memory device and at least one memory bank of the memory banks, without exchanging the data with the host, using at least one buffer fill command and at least one buffer copy command.

公开(公告)号：US20200035291A1

公开(公告)日：2020-01-30

申请号：US16251983

申请日：2019-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pavan Kumar Kasibhatla ,  Seong-il O ,  Hak-soo Yu

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4096 ,  G11C7/10 ,  G06F15/78

Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

公开(公告)号：US09600362B2

公开(公告)日：2017-03-21

申请号：US14699201

申请日：2015-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Uk-song Kang ,  Hak-soo Yu ,  Chul-woo Park

IPC: G06F11/10 ,  G11C11/406 ,  G11C29/52 ,  G06F3/06 ,  G11C11/40 ,  G11C29/04

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0652 ,  G06F3/0679 ,  G06F11/106 ,  G11C11/40 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: At least one refresh without scrubbing is performed on a corresponding portion of the memory device with a first frequency. In addition, at least one refresh with scrubbing is performed on a corresponding portion of the memory device with a second frequency less than the first frequency. Accordingly, refresh operations with data scrubbing are performed to prevent data error accumulation. Furthermore, refresh operations without data scrubbing are also performed to reduce undue power consumption from the data scrubbing.

公开(公告)号：US20140008598A1

公开(公告)日：2014-01-09

申请号：US14017856

申请日：2013-09-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-gyu Baek ,  Hong-sun Hwang ,  Hak-soo Yu ,  Chul-woo Park

IPC: H01L45/00

CPC classification number: H01L45/147 ,  G11C5/025 ,  G11C13/0002 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/14

Abstract: Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.

Abstract translation: 具有包括基于电阻器开关的逻辑电路的堆叠结构的半导体存储器件。 半导体存储器件包括第一导线，其包括第一线部分和第二线部分，其中第一线部分和第二线部分通过布置在第一线部分和第二线部分之间的中间区域彼此电分离， 连接到第一线部分并存储数据的第一可变电阻材料膜和控制第一线部分和第二线部分之间的电连接的第二可变电阻材料膜。