公开(公告)号：US12272423B2

公开(公告)日：2025-04-08

申请号：US17974940

申请日：2022-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sachin Suresh Upadhya ,  Eldho Pathiyakkara Thombra Mathew ,  Mayuresh Jyotindra Salelkar ,  Jinin So ,  Jonggeon Lee ,  Kyungsoo Kim

IPC: G11C7/10 ,  G11C7/22

Abstract: A method of operating a Near Memory Processing-Dual In-line Memory (NMP-DIMM) system, the method including: determining, by an adaptive latency module of the NMP-DIMM system, a synchronized read latency value for performing a read operation upon receiving a Multi-Purpose Register (MPR) read instruction from a host device communicatively connected with the NMP-DIMM system, wherein the MPR read instruction is received from the host device for training the NMP-DIMM system, wherein the synchronized read latency value is determined based on one or more read latency values associated with one or more memory units of the NMP-DIMM system; and synchronizing, by the adaptive latency module, one or more first type data paths and a second type data path in the NMP-DIMM system based on the determined synchronized read latency value.

公开(公告)号：US20230386534A1

公开(公告)日：2023-11-30

申请号：US17974940

申请日：2022-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sachin Suresh Upadhya ,  Eldho Pathiyakkara Thombra Mathew ,  Mayuresh Jyotindra Salelkar ,  Jinin So ,  Jonggeon Lee ,  Kyungsoo Kim

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1069 ,  G11C7/1066 ,  G11C7/227 ,  G11C7/1063

Abstract: A method of operating a Near Memory Processing-Dual In-line Memory (NMP-DIMM) system, the method including: determining, by an adaptive latency module of the NMP-DIMM system, a synchronized read latency value for performing a read operation upon receiving a Multi-Purpose Register (MPR) read instruction from a host device communicatively connected with the NMP-DIMM system, wherein the MPR read instruction is received from the host device for training the NMP-DIMM system, wherein the synchronized read latency value is determined based on one or more read latency values associated with one or more memory units of the NMP-DIMM system; and synchronizing, by the adaptive latency module, one or more first type data paths and a second type data path in the NMP-DIMM system based on the determined synchronized read latency value.

公开(公告)号：US11568907B2

公开(公告)日：2023-01-31

申请号：US17124056

申请日：2020-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eldho Pathiyakkara Thombra Mathew ,  Anirudh Birur Kiran ,  Hak-Soo Yu ,  Praful Ramesh Orakkan

IPC: G11C7/10 ,  G06F3/06 ,  G11C7/20 ,  G11C7/06

Abstract: A memory system includes a memory device including memory banks and a data bus management circuit and a host coupled to the memory device. The host includes a memory controller detecting at least one trigger initiated by at least one application for performing at least one operation on data stored within the memory device, the at least one operation including at least one of a data copy operation, and a data processing operation, and performing the at least one operation on the data within the memory device by enabling movement of the data between the data bus management circuit of the memory device and at least one memory bank of the memory banks, without exchanging the data with the host, using at least one buffer fill command and at least one buffer copy command.

公开(公告)号：US20230004489A1

公开(公告)日：2023-01-05

申请号：US17854772

申请日：2022-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Raghu Vamsi Krishna TALANKI ,  Eldho Pathiyakkara Thombra Mathew ,  Vishnu Charan Thummala ,  Vinod Kumar Srinivasan ,  Jin ln So ,  Jong-Geon Lee

IPC: G06F12/06

Abstract: A Near Memory Processing (NMP) dual in-line memory module (DIMM) for managing an address map is provided. The NMP DIMM includes: a static random-access memory (SRAM) provided on a Double Data Rate (DDR) interface; and an address management controller coupled to the SRAM, and configured to control the NMP DIMM to: receive a first indication from a host system to perform interface training for operating an SRAM space; perform the interface training using a first address map based on the first indication; receive a second indication from the host system indicating completion of the interface training for operating the SRAM space; switch from the first address map to a second address map for operating the SRAM space in response based on the second indication; and operate the SRAM space using the second address map.

公开(公告)号：US20220076717A1

公开(公告)日：2022-03-10

申请号：US17124056

申请日：2020-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eldho Pathiyakkara Thombra Mathew ,  Anirudh Birur Kiran ,  Hak-soo Yu ,  Praful Ramesh Orakkan

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/20

Abstract: A memory system includes a memory device including memory banks and a data bus management circuit and a host coupled to the memory device. The host includes a memory controller detecting at least one trigger initiated by at least one application for performing at least one operation on data stored within the memory device, the at least one operation including at least one of a data copy operation, and a data processing operation, and performing the at least one operation on the data within the memory device by enabling movement of the data between the data bus management circuit of the memory device and at least one memory bank of the memory banks, without exchanging the data with the host, using at least one buffer fill command and at least one buffer copy command.

公开(公告)号：US12045510B2

公开(公告)日：2024-07-23

申请号：US17874370

申请日：2022-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eldho Pathiyakkara Thombra Mathew ,  Prashant Vishwanath Mahendrakar ,  Jin In So ,  Jong-Geon Lee

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0607 ,  G06F3/0658 ,  G06F3/061 ,  G06F3/0683

Abstract: A Near Memory Processing (NMP) module including: a plurality of memory units; an Input/Output (I/O) interface configured to receive commands from a host system, wherein the host system includes a host memory controller configured to access the plurality of memory units; a decoder configured to decode the commands and generate a trigger; and an NMP memory controller configured to: receive the trigger from the decoder; and generate a signal in response to the trigger to synchronize the NMP module with the host system.

公开(公告)号：US11797440B2

公开(公告)日：2023-10-24

申请号：US17854772

申请日：2022-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Raghu Vamsi Krishna Talanki ,  Eldho Pathiyakkara Thombra Mathew ,  Vishnu Charan Thummala ,  Vinod Kumar Srinivasan ,  Jin In So ,  Jong-Geon Lee

IPC: G06F12/06

CPC classification number: G06F12/063 ,  G06F2212/206

Abstract: A Near Memory Processing (NMP) dual in-line memory module (DIMM) for managing an address map is provided. The NMP DIMM includes: a static random-access memory (SRAM) provided on a Double Data Rate (DDR) interface; and an address management controller coupled to the SRAM, and configured to control the NMP DIMM to: receive a first indication from a host system to perform interface training for operating an SRAM space; perform the interface training using a first address map based on the first indication; receive a second indication from the host system indicating completion of the interface training for operating the SRAM space; switch from the first address map to a second address map for operating the SRAM space in response based on the second indication; and operate the SRAM space using the second address map.

公开(公告)号：US11016781B2

公开(公告)日：2021-05-25

申请号：US16563053

申请日：2019-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eldho Pathiyakkara Thombra Mathew ,  Yash Jajoo ,  Jai Babu Mahankud ,  Hari Babu Chimakurthy

IPC: G06F9/4401 ,  G06F12/02 ,  G11C8/12 ,  G06F3/06 ,  G11C11/409

Abstract: Some example embodiments presented herein provide methods and memory modules for configuring vendor-specific registers in the memory modules to enable and/or disable vendor-specific functionality. The vendor-specific register space may be organized by a vendor-specific logic and accessed by a standard memory access command received while the memory is in a programming mode. A write command may be received from a host device to switch the memory module to a programming mode, and the memory module may be switched to the programming mode responsive to the command. A memory write command may be received from the host device involving the memory module switched to the programming mode, and a vendor-specific register may be configured based on the memory write command and the organization of the vendor-specific register indicated by the vendor-specific logic.