公开(公告)号：US11797440B2

公开(公告)日：2023-10-24

申请号：US17854772

申请日：2022-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Raghu Vamsi Krishna Talanki ,  Eldho Pathiyakkara Thombra Mathew ,  Vishnu Charan Thummala ,  Vinod Kumar Srinivasan ,  Jin In So ,  Jong-Geon Lee

IPC: G06F12/06

CPC classification number: G06F12/063 ,  G06F2212/206

Abstract: A Near Memory Processing (NMP) dual in-line memory module (DIMM) for managing an address map is provided. The NMP DIMM includes: a static random-access memory (SRAM) provided on a Double Data Rate (DDR) interface; and an address management controller coupled to the SRAM, and configured to control the NMP DIMM to: receive a first indication from a host system to perform interface training for operating an SRAM space; perform the interface training using a first address map based on the first indication; receive a second indication from the host system indicating completion of the interface training for operating the SRAM space; switch from the first address map to a second address map for operating the SRAM space in response based on the second indication; and operate the SRAM space using the second address map.

公开(公告)号：US20230004489A1

公开(公告)日：2023-01-05

申请号：US17854772

申请日：2022-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Raghu Vamsi Krishna TALANKI ,  Eldho Pathiyakkara Thombra Mathew ,  Vishnu Charan Thummala ,  Vinod Kumar Srinivasan ,  Jin ln So ,  Jong-Geon Lee

IPC: G06F12/06

Abstract: A Near Memory Processing (NMP) dual in-line memory module (DIMM) for managing an address map is provided. The NMP DIMM includes: a static random-access memory (SRAM) provided on a Double Data Rate (DDR) interface; and an address management controller coupled to the SRAM, and configured to control the NMP DIMM to: receive a first indication from a host system to perform interface training for operating an SRAM space; perform the interface training using a first address map based on the first indication; receive a second indication from the host system indicating completion of the interface training for operating the SRAM space; switch from the first address map to a second address map for operating the SRAM space in response based on the second indication; and operate the SRAM space using the second address map.