公开(公告)号：US20220173008A1

公开(公告)日：2022-06-02

申请号：US17332471

申请日：2021-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunjae KIM ,  Eunsil KANG ,  Daehyun KIM ,  Sunkyoung SEO

IPC: H01L23/31 ,  H01L25/18 ,  H01L25/065 ,  H01L23/29 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip on a wiring structure, a plurality of internal terminals between the wiring structure and the first semiconductor chip; a high thermal conductivity layer is between the wiring structure and the first semiconductor chip; and an encapsulator on the high thermal conductivity layer and contacting the second semiconductor chip. Sidewalls of at least the wiring structure and the encapsulator are substantially coplanar.

公开(公告)号：US20220165608A1

公开(公告)日：2022-05-26

申请号：US17574665

申请日：2022-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hyun IM ,  Kibum LEE ,  Daehyun KIM ,  Ju Hyung WE ,  Sungmi YOON

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/02 ,  H01L27/108 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/146 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a semiconductor substrate that includes a trench defining an active region; a buried dielectric pattern in the trench; a silicon oxide layer between the buried dielectric pattern and an inner wall of the trench; and a polycrystalline silicon layer between the silicon oxide layer and the inner wall of the trench, wherein the polycrystalline silicon layer has a first surface in contact with the semiconductor substrate and a second surface in contact with the silicon oxide layer, and wherein the second surface includes a plurality of silicon grains that are uniformly distributed.

公开(公告)号：US20210288353A1

公开(公告)日：2021-09-16

申请号：US17196094

申请日：2021-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Manohar GOTTAPU ,  Arijit GUHA ,  Shashishekara Parampalli ADIGA ,  Daehyun KIM ,  Taedong GOH ,  Youngho RYU

IPC: H01M10/42 ,  H01M10/48 ,  G01R31/3842 ,  G01R31/367 ,  H01M10/44

Abstract: Methods and electronic devices for estimating state of charge (SOC) of a battery pack. Various embodiments provide a model comprising an (electrical) equivalent circuit model, an electrochemical (thermal) model, and a (convective) thermal model. The model estimates parameters pertaining to each cell of the battery pack individually, and determines the variations in the values of the parameters among each of the cells of the battery pack. The parameters include capacity, temperature current, voltage, and SOC. The parameters are computed based on at current drawn by the battery pack, electrochemical parameters, thermal parameters, and cell internal and connection resistances of the individual cells. Various embodiments compute battery pack uptime, chargeable capacity of the battery pack and SOC of the battery pack, based on the values of the parameters.

公开(公告)号：US20210250651A1

公开(公告)日：2021-08-12

申请号：US16973938

申请日：2019-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjun KIM ,  Daehyun KIM ,  Hayeon YOO ,  Sanghee LEE ,  Manchul HAN

IPC: H04N21/466 ,  H04N21/45

Abstract: Disclosed is a display apparatus comprising: a display; a user input unit; and a processor configured to identify a user's viewing time based on a user's viewing history, create a list of content to be provided within the identified viewing time based on the viewing history and display the created content list on the display, and select at least one piece of content in the content list for viewing schedule based on a user input through the user input unit.

公开(公告)号：US20210132790A1

公开(公告)日：2021-05-06

申请号：US16492332

申请日：2018-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soyoung KIM ,  Daehyun KIM ,  Minsik KIM ,  Jongmoo LEE ,  Geon-Soo KIM ,  Jin-Wan AN ,  Ji-Woo LEE ,  Hyun-Suk CHOI

IPC: G06F3/0488 ,  G06F3/14 ,  G06F3/16 ,  G06F3/01 ,  G06F3/041 ,  G06F3/0484

Abstract: Provided are an electronic device and a screen display method of the electronic device. More specifically, provided are an electronic device for providing an extension function to a second area according to a characteristic of a characteristic area in first and second areas of an extended touch screen, and a screen display method of the electronic device. Some of the disclosed embodiments provide an electronic device for providing an extension function to a second area according to a characteristic of a characteristic area of an application screen in first and second areas divided by a trigger in an extended touch screen. In addition thereto, various other embodiments are also possible.

公开(公告)号：US20250123755A1

公开(公告)日：2025-04-17

申请号：US18670908

申请日：2024-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daehyun KIM ,  Suhyun KIM ,  Ikkyun PARK ,  Hyunju YI

IPC: G06F3/06

Abstract: An embodiment of the method includes transferring a first read command corresponding to a first cell region of the memory device through a first channel, receiving first data, read from the first cell region, from the memory device through a second channel physically separated from the first channel, transferring a status information request command through the first channel, the status information request command request the transfer of status information about a second cell region of the memory device, receiving the status information about the second cell region from the memory device through the first channel, and transferring a second read command corresponding to the second cell region of the memory device through the first channel, at least a portion of a period in which the status information is received through the first channel overlaps a period where the first data is received through the second channel.

公开(公告)号：US20240364147A1

公开(公告)日：2024-10-31

申请号：US18765065

申请日：2024-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beomwoo GU ,  Daehyun KIM ,  Jaehyun PARK ,  Kangho BYUN ,  Sungku YEO ,  Youngho RYU

IPC: H02J50/90 ,  H02J50/12 ,  H02J50/80

CPC classification number: H02J50/90 ,  H02J50/12 ,  H02J50/80

Abstract: A wireless power transmission device is provided. The wireless power transmission device includes a transmission coil including a first member, which has one end and the other end forming a first angle with a plane, and a second member, which is arranged on the plane and is connected to each of the one end and the other end of the first member, an impedance sensor for outputting a voltage value corresponding to an impedance change amount of a resonance circuit, which includes the transmission coil, a magnetic body having a side surface that is dented, the dented side surface facing a portion of the transmission coil, a motor for moving the magnetic body, memory storing one or more computer programs, and one or more processors communicatively coupled to the memory, wherein the one or more computer programs include computer-executable instructions that, when executed by the one or more processors individually or collectively, cause the wireless power transmission device to receive the output voltage value from the impedance sensor, calculate the difference value between a reference voltage value and the received voltage value, determine control information about the motor on the basis of the calculated difference value, and drive the motor through the determined control information so as to control the distance between the magnetic body and the portion of the transmission coil.

公开(公告)号：US20240292597A1

公开(公告)日：2024-08-29

申请号：US18528621

申请日：2023-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghwan HUH ,  Daehyun KIM ,  Yeajin NA ,  Junsik YU ,  Taekyung YOON ,  Yoojin JEONG ,  Yongjun CHOI

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/485 ,  H10B12/482

Abstract: Described is a semiconductor device comprising an active pattern, an additional active layer on the active pattern, and a gate structure that runs across the active pattern. The additional active layer includes a bottom surface connected to a sidewall of the active pattern and an upper curved surface at a level higher than a level of the bottom surface. A lattice contact of the additional active layer is different from that of the active pattern.

公开(公告)号：US20240222303A1

公开(公告)日：2024-07-04

申请号：US18226589

申请日：2023-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daehyun KIM ,  KUNSIL LEE

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/14 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/11 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L25/18 ,  H01L2224/05073 ,  H01L2224/05144 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/0613 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1413 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first substrate having first pads on a first surface of the first substrate, a second substrate on the first substrate and having a plurality of second pads on a second surface of the second substrate, and connection terminals between the first substrate and the second substrate and correspondingly coupling the first pad to the second pads. Each of the connection terminals has a first major axis and a first minor axis that are parallel to the first surface of the first substrate and are orthogonal to each other. When viewed in a plan view, the first minor axis of each of the connection terminals is directed toward a center of the first substrate.

公开(公告)号：US20240222217A1

公开(公告)日：2024-07-04

申请号：US18593381

申请日：2024-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunjae KIM ,  Eunsil KANG ,  Daehyun KIM ,  Sunkyoung SEO

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L21/56

CPC classification number: H01L23/3192 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L21/561 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0557 ,  H01L2224/06519 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/29499 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161

Abstract: A semiconductor package includes a first semiconductor chip on a wiring structure, a plurality of internal terminals between the wiring structure and the first semiconductor chip; a high thermal conductivity layer is between the wiring structure and the first semiconductor chip; and an encapsulator on the high thermal conductivity layer and contacting the second semiconductor chip. Sidewalls of at least the wiring structure and the encapsulator are substantially coplanar.