公开(公告)号：US20200381414A1

公开(公告)日：2020-12-03

申请号：US16997732

申请日：2020-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Titash Rakshit ,  Borna J. Obradovic ,  Chris Bowen ,  Mark S. Rodder

IPC: H01L27/02 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/822 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L21/84 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/06 ,  H01L27/092 ,  H01L29/04 ,  H01L29/16 ,  H01L29/47

Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include polycrystalline silicon. The upper metal routing layer M3 or higher may include cobalt.

公开(公告)号：US20180254350A1

公开(公告)日：2018-09-06

申请号：US15656898

申请日：2017-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Rwik Sengupta ,  Chris Bowen

IPC: H01L29/78 ,  H03K19/20 ,  H01L27/11

CPC classification number: H01L29/78391 ,  H01L27/1104 ,  H03K19/20

Abstract: A system of unipolar digital logic. Ferroelectric field effect transistors having channels of a first polarity, are combined, in circuits, with simple field effect transistors having channels of the same polarity, to form logic gates and/or memory cells.

公开(公告)号：US09893187B2

公开(公告)日：2018-02-13

申请号：US15342008

申请日：2016-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Chris Bowen ,  Kiyotaka Imai ,  Mark S. Rodder

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7869

Abstract: A method for fabricating a fin field effect transistor (finFET) device with a strained channel. During fabrication, after the fin is formed, a dummy gate is deposited on the fin, and processed, e.g., by plasma doping and annealing, to cause stress in the dummy gate. Deep source drain (SD) recesses are formed, resulting in strain in the channel, and SD structures are formed to anchor the ends of the fin. The dummy gate is then removed.

公开(公告)号：US09263549B2

公开(公告)日：2016-02-16

申请号：US13865478

申请日：2013-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Chris Bowen

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66537 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a field effect transistor includes forming a punchthrough region having a first conductivity type in a substrate, forming an epitaxial layer having the first conductivity type on the substrate, patterning the epitaxial layer to form a fin that protrudes from the substrate, forming a dummy gate and gate sidewall spacers on the fin defining preliminary source and drain regions of the fin on opposite sides of the dummy gate, removing the preliminary source and drain regions of the fin, implanting second conductivity type dopant atoms into exposed portions of the substrate and the punchthrough region, and forming source and drain regions having the second conductivity type on opposite sides of the dummy gate and the gate sidewall spacers.

Abstract translation: 形成场效应晶体管的方法包括在衬底中形成具有第一导电类型的穿透区域，在衬底上形成具有第一导电类型的外延层，图案化外延层以形成从衬底突出的鳍状物，形成 翅片上的虚拟栅极和栅极侧壁间隔物，其限定了在虚拟栅极的相对侧上的鳍片的初始源极和漏极区域，去除鳍片的初始源极和漏极区域，将第二导电类型掺杂剂原子注入衬底的暴露部分 并且穿透区域，并且在伪栅极和栅极侧壁间隔物的相对侧上形成具有第二导电类型的源极和漏极区域。

公开(公告)号：US20140312393A1

公开(公告)日：2014-10-23

申请号：US13865478

申请日：2013-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mark S. Rodder ,  Chris Bowen

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66537 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a field effect transistor includes forming a punchthrough region having a first conductivity type in a substrate, forming an epitaxial layer having the first conductivity type on the substrate, patterning the epitaxial layer to form a fin that protrudes from the substrate, forming a dummy gate and gate sidewall spacers on the fin defining preliminary source and drain regions of the fin on opposite sides of the dummy gate, removing the preliminary source and drain regions of the fin, implanting second conductivity type dopant atoms into exposed portions of the substrate and the punchthrough region, and forming source and drain regions having the second conductivity type on opposite sides of the dummy gate and the gate sidewall spacers.

Abstract translation: 形成场效应晶体管的方法包括在衬底中形成具有第一导电类型的穿透区域，在衬底上形成具有第一导电类型的外延层，图案化外延层以形成从衬底突出的鳍状物，形成 翅片上的虚拟栅极和栅极侧壁间隔物，其限定了在虚拟栅极的相对侧上的鳍片的初始源极和漏极区域，去除鳍片的初始源极和漏极区域，将第二导电类型掺杂剂原子注入衬底的暴露部分 并且穿透区域，并且在伪栅极和栅极侧壁间隔物的相对侧上形成具有第二导电类型的源极和漏极区域。