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    MEMORY DEVICE, SYSTEM AND METHOD EMPLOYING MULTIPHASE CLOCK
    11.
    发明公开
    MEMORY DEVICE, SYSTEM AND METHOD EMPLOYING MULTIPHASE CLOCK 审中-公开

    公开(公告)号：US20230368855A1

    公开(公告)日：2023-11-16

    申请号：US18061764

    申请日：2022-12-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyochang Kim ,  Changsik Yoo

    IPC: G11C29/02 ,  G11C7/10 ,  G11C7/06 ,  G11C7/22

    CPC classification number: G11C29/023 ,  G11C7/1012 ,  G11C7/062 ,  G11C7/22

    Abstract: A memory device includes a DC conversion circuit that receives a first edge-triggered phase signal having first pulses each extending from a rising edge of a first phase signal of a multiphase clock to a later rising edge of a second phase signal of the multiphase clock and a second edge-triggered phase signal having second pulses each extending from a rising edge of the second phase signal to a later rising edge of the first phase signal, and outputting a first voltage corresponding to the first edge-triggered phase signal and a second voltage corresponding to the second edge-triggered phase signal, a comparator that compares the first voltage with the second voltage, control logic that generates a control code corresponding to an output value from the comparator, and a delay cell that delays the second phase signal according to the control code.

    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
    12.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20230307022A1

    公开(公告)日：2023-09-28

    申请号：US18143967

    申请日：2023-05-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hojun Yoon ,  Youngchul Cho ,  Youngdon Choi ,  Changsik Yoo ,  Junghwan Choi

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1084

    Abstract: A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.

    Serializer and memory device including the same
    14.
    发明授权
    Serializer and memory device including the same 有权

    公开(公告)号：US11615824B2

    公开(公告)日：2023-03-28

    申请号：US17536282

    申请日：2021-11-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changsik Yoo ,  Hyunah An

    IPC: G11C7/22 ,  G11C5/14 ,  G11C7/10

    Abstract: A serializer includes data input circuits configured to receive N-number of pieces of data in parallel, where N is an even number, data connection circuits configured to receive internal clock signals having different phases in different arrangements, and data output circuits configured to output the N-number of pieces of data in sequence in a single cycle of each of the internal clock signals, wherein the data connection circuits operate the data output circuits such that the data output circuits, in response to the internal clock signals, output corresponding data of the N-number of pieces of data in an enable period in the single cycle and have a high impedance state in a disable period in the single cycle.

    MEMORY DEVICE HAVING CELL OVER PERIPHERY STRUCTURE AND SEMICONDUCTOR DEVICE HAVING BONDING STRUCTURE
    15.
    发明申请
    MEMORY DEVICE HAVING CELL OVER PERIPHERY STRUCTURE AND SEMICONDUCTOR DEVICE HAVING BONDING STRUCTURE 有权

    公开(公告)号：US20250140332A1

    公开(公告)日：2025-05-01

    申请号：US18799907

    申请日：2024-08-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Changyoung Lee ,  Sanghoon Jung ,  Changsik Yoo

    IPC: G11C29/12 ,  H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

    Abstract: An example memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a memory cell array, a first bonding pad, and a first test pad. The second semiconductor layer is disposed with respect to the first semiconductor layer in a vertical direction, and includes a peripheral circuit, a second bonding pad connected to the first bonding pad, a second test pad connected to the first test pad, and a test circuit. The test circuit checks a connection state of the first and second bonding pads. The test circuit receives a first test signal through the first and second test pads, generates a first test result signal representing a first misalignment between the first and second bonding pads based on the first test signal, and compensates an operation of the peripheral circuit based on the first test result signal.

    Semiconductor device with adjustment of phase of data signal and clock signals, and memory system including the same
    16.
    发明授权
    Semiconductor device with adjustment of phase of data signal and clock signals, and memory system including the same 有权

    公开(公告)号：US12205668B2

    公开(公告)日：2025-01-21

    申请号：US17722805

    申请日：2022-04-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaemin Choi ,  Yonghun Kim ,  Jaewoo Jeong ,  Kyungryun Kim ,  Yoochang Sung ,  Changsik Yoo

    IPC: G11C7/10

    Abstract: A semiconductor device includes: a plurality of pads connected to a memory device receiving a data signal using first to fourth clock signals having different phases; a data transmission/reception circuit inputting and outputting the data signal to a plurality of data pads of the plurality of pads and including a data delay cell adjusting a phase of the data signal; a clock output circuit outputting first to fourth clock signals to a plurality of clock pads of the plurality of pads and including first to fourth clock delay cells adjusting phases of the first to fourth clock signals; and a controller adjusting a delay amount of at least one of the first to fourth clock delay cells and the data delay cell so that each of the first to fourth clock signals is aligned with the data signal in the memory device.

    Data processing device and memory system including the same
    19.
    发明授权
    Data processing device and memory system including the same 有权

    公开(公告)号：US11627021B2

    公开(公告)日：2023-04-11

    申请号：US17563406

    申请日：2021-12-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaewoo Park ,  Youngdon Choi ,  Junghwan Choi ,  Changsik Yoo

    IPC: H04L25/02 ,  H04L25/14 ,  H04L25/49

    Abstract: Provided are a memory device and a memory system including the same. The memory device may include a data bus inversion (DBI) mode selector configured to select a first multi-bit DBI signal from among a plurality of multi-bit DBI signals respectively corresponding to a plurality of DBI modes according to multi-bit data; a multi-mode DBI encoder configured to generate encoded multi-bit data by DBI encoding the multi-bit data according to the first multi-bit DBI signal; and a transceiver configured to transmit a data symbol corresponding to the encoded multi-bit data through a data channel and transmit a DBI symbol corresponding to the first multi-bit DBI signal through a DBI channel.

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