公开(公告)号：US11238921B2

公开(公告)日：2022-02-01

申请号：US16848418

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Buyeon Lee ,  Taegyeong Kim ,  Taesung Kim ,  Byongmo Moon

IPC: G11C11/4093 ,  G06F3/06 ,  H03K19/00

Abstract: A memory device includes a pad region having a flag pad separated from an external host, and a signal pad connected to the external host. A bank region is provided having a plurality of memory cells therein. An on-die-termination (ODT) setting circuit is provided, which is configured to receive a control command including first data corresponding to termination resistance requested by the host, and a ODT enable signal. The setting circuit is configured to generate second data corresponding to the ODT resistance. An ODT enable circuit is provided, which is configured to output an ODT flag signal to the flag pad, in response to the control command and the ODT enable signal. A resistor circuit is provided, which is configured to connect the ODT resistance to the signal pad using the second data.

公开(公告)号：US11189332B2

公开(公告)日：2021-11-30

申请号：US16842891

申请日：2020-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaewoo Jeong ,  Byongmo Moon

IPC: G11C11/4074 ,  G11C11/4076 ,  G11C11/4094 ,  G11C29/12 ,  G11C11/4091

Abstract: A memory device includes a memory cell array including a plurality of memory cells storing data, a sense amplifier connected to the memory cell array, and a voltage controller. The voltage controller includes a voltage driver that generates a control signal and an overdrive controller that generates an overdrive control signal that regulates the generating of the control signal in response to at least one of a result of a comparison between the control signal and a reference voltage, and process, voltage, temperature (PVT) information. The voltage driver adjusts the control signal in response to the overdrive control signal to generate an overdriven control signal and outputs the overdriven control signal to the sense amplifier.

公开(公告)号：US20250119131A1

公开(公告)日：2025-04-10

申请号：US18626494

申请日：2024-04-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byongmo Moon ,  Seongook Jung ,  Hohyun Chae ,  Taeryeong Kim ,  Jeonghyeok You

IPC: H03K5/134 ,  H03K5/00 ,  H03L7/081

Abstract: A circuit configured to detect a threshold voltage includes a first delay circuit, a second delay circuit and a controller. The first delay circuit has a first sensitivity to threshold voltage of a transistor. The first delay circuit may be configured to generate a first output signal delayed with respect to the input signal by a first delay time that changes depending on the digital control code. The second delay circuit has a second sensitivity that is higher than the first sensitivity. The second delay circuit may be configured to generate a second output signal delayed with respect to the input signal by a second delay time. The controller may compare the first and second output signals and may generate a digital output code corresponding to the digital control code when the first delay time is equal to the second delay time to indicate the threshold voltage of the transistor.

公开(公告)号：US11574670B2

公开(公告)日：2023-02-07

申请号：US17690137

申请日：2022-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byongmo Moon ,  Beomyong Kil ,  Jihye Kim

IPC: G11C5/14 ,  G11C11/4074 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/409

Abstract: A memory device includes: first power pins in a first power area and configured to receive a first power voltage; data pins configured to transmit or receive data signals, the data pins being arranged in a first region and in a second region each including the first power area; control pins configured to transmit or receive control signals in the first region and in the second region; second power pins in a second power area between the first region and the second region and configured to receive a second power voltage different from the first power voltage; and ground pins in the second power area and configured to receive a ground voltage.

公开(公告)号：US11488646B2

公开(公告)日：2022-11-01

申请号：US16909177

申请日：2020-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byongmo Moon

IPC: G11C7/22 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4074

Abstract: An encoder includes an encoding unit configured to receive 2n-bit read data and to generate 2m-bit read data, and an output driver configured to input m-bit first read data of the 2m-bit read data, to transmit voltage and/or current a first number of times corresponding to a number of first bits indicating a first state included in the m-bit first read data or to transmit current corresponding to the number of first bits during an activation period of a clock signal, and to transmit the voltage and/or the current a second number of times corresponding to a number of second bits indicating the first state included in m-bit second read data of the 2m-bit read data or to transmit current corresponding to the number of second bits during a deactivation period of the clock signal, wherein n is at least 2 and m is at least 3.

公开(公告)号：US11309014B2

公开(公告)日：2022-04-19

申请号：US17143619

申请日：2021-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byongmo Moon ,  Sungoh Ahn

IPC: G11C11/40 ,  G11C11/4074 ,  H01L25/18 ,  H01L23/00 ,  G11C11/4096 ,  G06F1/10 ,  G06F1/26 ,  G11C11/4093

Abstract: Disclosed is a memory device, which includes a buffer die that outputs a first power supply voltage to a first through-substrate via (e.g., through-silicon via (TSV)) and receives a small swing data signal from a second TSV generated based on the first power supply voltage, and a core die that is electrically connected to the buffer die through the first and second TSVs, includes a first cell capacitor electrically connected to the first TSV and configured to block a first noise introduced to the first power supply voltage received through the first TSV. The core die outputs the small swing data signal to the second TSV.

公开(公告)号：US20210142834A1

公开(公告)日：2021-05-13

申请号：US16909177

申请日：2020-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byongmo Moon

IPC: G11C7/22 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408

Abstract: An encoder includes an encoding unit configured to receive 2n-bit read data and to generate 2m-bit read data, and an output driver configured to input m-bit first read data of the 2m-bit read data, to transmit voltage and/or current a first number of times corresponding to a number of first bits indicating a first state included in the m-bit first read data or to transmit current corresponding to the number of first bits during an activation period of a clock signal, and to transmit the voltage and/or the current a second number of times corresponding to a number of second bits indicating the first state included in m-bit second read data of the 2m-bit read data or to transmit current corresponding to the number of second bits during a deactivation period of the clock signal, wherein n is at least 2 and m is at least 3.

公开(公告)号：US20210020227A1

公开(公告)日：2021-01-21

申请号：US16848418

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Buyeon Lee ,  Taegyeong Kim ,  Taesung Kim ,  Byongmo Moon

IPC: G11C11/4093 ,  H03K19/00 ,  G06F3/06

Abstract: A memory device includes a pad region having a flag pad separated from an external host, and a signal pad connected to the external host. A bank region is provided having a plurality of memory cells therein. An on-die-termination (ODT) setting circuit is provided, which is configured to receive a control command including first data corresponding to termination resistance requested by the host, and a ODT enable signal. The setting circuit is configured to generate second data corresponding to the ODT resistance. An ODT enable circuit is provided, which is configured to output an ODT flag signal to the flag pad, in response to the control command and the ODT enable signal. A resistor circuit is provided, which is configured to connect the ODT resistance to the signal pad using the second data.