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    Memory device for reducing resources used for training
    4.
    发明授权
    Memory device for reducing resources used for training 有权

    公开(公告)号：US11309013B2

    公开(公告)日：2022-04-19

    申请号：US17130493

    申请日：2020-12-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byongmo Moon ,  Beomyong Kil ,  Jihye Kim

    IPC: G11C5/14 ,  G11C11/4074 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/409

    Abstract: A memory device includes: first power pins in a first power area and configured to receive a first power voltage; data pins configured to transmit or receive data signals, the data pins being arranged in a first region and in a second region each including the first power area; control pins configured to transmit or receive control signals in the first region and in the second region; second power pins in a second power area between the first region and the second region and configured to receive a second power voltage different from the first power voltage; and ground pins in the second power area and configured to receive a ground voltage.

    Apparatus for correcting error of clock signal
    5.
    发明授权
    Apparatus for correcting error of clock signal 有权

    公开(公告)号：US12231528B2

    公开(公告)日：2025-02-18

    申请号：US18197079

    申请日：2023-05-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byongmo Moon ,  Jeonghyeok You ,  Seongook Jung ,  Taeryeong Kim ,  Hohyun Chae

    IPC: H04L7/00 ,  G06F1/04 ,  H03K3/017 ,  H03K3/037 ,  H03K5/14 ,  H03K5/00 ,  H03K19/20

    Abstract: An apparatus for correcting an error of a clock signal may include a phase adjuster that corrects an error of half-rate clock signals based on an error correction signal to output an error-corrected clock signal, a phase splitter that outputs quadrature clock signals from the error-corrected clock signal, an error detector that outputs an internal clock signal based on one of the quadrature clock signals, selects two quadrature clock signals among the quadrature clock signals based on a clock selection signal, and detects errors of the two quadrature clock signals based on an error check signal to output a correction request signal, and a controller that outputs a mode selection signal and the clock selection signal based on the internal clock signal and that outputs the error correction signal and the error check signal based on the mode selection signal, the clock selection signal, and the correction request signal.

    Memory device transmitting and receiving data at high speed and low power
    6.
    发明授权
    Memory device transmitting and receiving data at high speed and low power 有权

    公开(公告)号：US11295808B2

    公开(公告)日：2022-04-05

    申请号：US17084345

    申请日：2020-10-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byongmo Moon ,  Jihye Kim ,  Je Min Ryu ,  Beomyong Kil ,  Sungoh Ahn

    IPC: G11C11/4076 ,  G11C11/4093 ,  G06F3/06 ,  G11C11/4096 ,  H01L25/18

    Abstract: A memory device includes a control logic circuit, a write data strobe signal divider, a data transceiver, and a memory cell array. The control logic circuit generates a reset signal before a write data strobe signal provided from a memory controller starts to toggle. The write data strobe signal divider generates internal write data strobe signals that toggle depending on toggling of the write data strobe signal, the internal write data strobe signals toggling with different phases, respectively. The control logic circuit initializes the internal write data strobe signals to given values in response to the reset signal. The data transceiver receives write data provided from the memory controller based on the internal write data strobe signals. The memory cell array stores the received write data.

    Memory device, operating method of the memory device, and memory system including the same
    8.
    发明授权
    Memory device, operating method of the memory device, and memory system including the same 有权

    公开(公告)号：US12210777B2

    公开(公告)日：2025-01-28

    申请号：US18242250

    申请日：2023-09-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyungmin Kim ,  Byongmo Moon

    IPC: G06F3/06

    Abstract: In some embodiments, a memory device includes a data sampler configured to sample a data signal based on a write data strobe signal, a measuring circuit configured to measure a temperature-based delay variation and a voltage-based delay variation of a transfer path of the write data strobe signal, a storage circuit configured to store a first coefficient code regulating a reference-based delay variation on the transfer path, a temperature sensor configured to sense the temperature of the transfer path, a monitoring circuit configured to generate a second coefficient code by comparing the sensed temperature, the temperature-based delay variation, the voltage-based delay variation, and the reference-based delay variation with each other, a reference voltage generator configured to generate a reference voltage, a voltage regulator configured to generate a regulation voltage, and a write data strobe signal transfer circuit configured to transfer the write data strobe signal to the data sampler.

    ENCODERS, DECODERS, AND SEMICONDUCTOR MEMORY DEVICES INCLUDING THE SAME
    9.
    发明申请
    ENCODERS, DECODERS, AND SEMICONDUCTOR MEMORY DEVICES INCLUDING THE SAME 有权

    公开(公告)号：US20230018451A1

    公开(公告)日：2023-01-19

    申请号：US17954860

    申请日：2022-09-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byongmo Moon

    IPC: G11C7/22 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4074

    Abstract: An encoder includes an encoding unit configured to receive 2n-bit read data and to generate 2m-bit read data, and an output driver configured to input m-bit first read data of the 2m-bit read data, to transmit voltage and/or current a first number of times corresponding to a number of first bits indicating a first state included in the m-bit first read data or to transmit current corresponding to the number of first bits during an activation period of a clock signal, and to transmit the voltage and/or the current a second number of times corresponding to a number of second bits indicating the first state included in m-bit second read data of the 2m-bit read data or to transmit current corresponding to the number of second bits during a deactivation period of the clock signal, wherein n is at least 2 and m is at least 3.

    Transmitter and receiver for low power input/output and memory system including the same
    10.
    发明授权
    Transmitter and receiver for low power input/output and memory system including the same 有权

    公开(公告)号：US11356098B2

    公开(公告)日：2022-06-07

    申请号：US17353917

    申请日：2021-06-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byongmo Moon ,  Jiyoung Kim ,  Seongook Jung ,  Jongsoo Lee

    IPC: G11C7/10 ,  H03K19/173 ,  H03K19/0175 ,  G11C7/22 ,  H03K19/17788 ,  G11C7/14 ,  H03K19/017

    Abstract: A transmitter includes a multiplexer, control logic and a voltage mode driver. The multiplexer generates a plurality of time-interleaved data signals based on a plurality of input data signals and multi-phase clock signals. The plurality of input data signals are input in parallel. Each of the plurality of input data signals is a binary signal and has two voltage levels that are different from each other. The control logic generates at least one pull-down control signal and a plurality of pull-up control signals based on the plurality of time-interleaved data signals. Each of the plurality of pull-up control signals has a voltage level that is temporarily boosted. The voltage mode driver generates an output data signal based on the at least one pull-down control signal and the plurality of pull-up control signals. The output data signal is a duobinary signal and has three voltage levels that are different from each other.

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