公开(公告)号：US20250119131A1

公开(公告)日：2025-04-10

申请号：US18626494

申请日：2024-04-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byongmo Moon ,  Seongook Jung ,  Hohyun Chae ,  Taeryeong Kim ,  Jeonghyeok You

IPC: H03K5/134 ,  H03K5/00 ,  H03L7/081

Abstract: A circuit configured to detect a threshold voltage includes a first delay circuit, a second delay circuit and a controller. The first delay circuit has a first sensitivity to threshold voltage of a transistor. The first delay circuit may be configured to generate a first output signal delayed with respect to the input signal by a first delay time that changes depending on the digital control code. The second delay circuit has a second sensitivity that is higher than the first sensitivity. The second delay circuit may be configured to generate a second output signal delayed with respect to the input signal by a second delay time. The controller may compare the first and second output signals and may generate a digital output code corresponding to the digital control code when the first delay time is equal to the second delay time to indicate the threshold voltage of the transistor.

公开(公告)号：US12231528B2

公开(公告)日：2025-02-18

申请号：US18197079

申请日：2023-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byongmo Moon ,  Jeonghyeok You ,  Seongook Jung ,  Taeryeong Kim ,  Hohyun Chae

IPC: H04L7/00 ,  G06F1/04 ,  H03K3/017 ,  H03K3/037 ,  H03K5/14 ,  H03K5/00 ,  H03K19/20

Abstract: An apparatus for correcting an error of a clock signal may include a phase adjuster that corrects an error of half-rate clock signals based on an error correction signal to output an error-corrected clock signal, a phase splitter that outputs quadrature clock signals from the error-corrected clock signal, an error detector that outputs an internal clock signal based on one of the quadrature clock signals, selects two quadrature clock signals among the quadrature clock signals based on a clock selection signal, and detects errors of the two quadrature clock signals based on an error check signal to output a correction request signal, and a controller that outputs a mode selection signal and the clock selection signal based on the internal clock signal and that outputs the error correction signal and the error check signal based on the mode selection signal, the clock selection signal, and the correction request signal.

公开(公告)号：US20240146498A1

公开(公告)日：2024-05-02

申请号：US18197079

申请日：2023-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYONGMO MOON ,  Jeonghyeok YOU ,  Seongook JUNG ,  Taeryeong KIM ,  Hohyun Chae

IPC: H04L7/00 ,  G06F1/04 ,  H03K3/017 ,  H03K3/037 ,  H03K5/14

CPC classification number: H04L7/0016 ,  G06F1/04 ,  H03K3/017 ,  H03K3/037 ,  H03K5/14 ,  H03K19/20

Abstract: An apparatus for correcting an error of a clock signal may include a phase adjuster that corrects an error of half-rate clock signals based on an error correction signal to output an error-corrected clock signal, a phase splitter that outputs quadrature clock signals from the error-corrected clock signal, an error detector that outputs an internal clock signal based on one of the quadrature clock signals, selects two quadrature clock signals among the quadrature clock signals based on a clock selection signal, and detects errors of the two quadrature clock signals based on an error check signal to output a correction request signal, and a controller that outputs a mode selection signal and the clock selection signal based on the internal clock signal and that outputs the error correction signal and the error check signal based on the mode selection signal, the clock selection signal, and the correction request signal.