公开(公告)号：US20210110860A1

公开(公告)日：2021-04-15

申请号：US16842891

申请日：2020-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAEWOO JEONG ,  BYONGMO MOON

IPC: G11C11/4074 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C29/12

Abstract: A memory device includes a memory cell array including a plurality of memory cells storing data, a sense amplifier connected to the memory cell array, and a voltage controller. The voltage controller includes a voltage driver that generates a control signal and an overdrive controller that generates an overdrive control signal that regulates the generating of the control signal in response to at least one of a result of a comparison between the control signal and a reference voltage, and process, voltage, temperature (PVT) information. The voltage driver adjusts the control signal in response to the overdrive control signal to generate an overdriven control signal and outputs the overdriven control signal to the sense amplifier.

公开(公告)号：US20230361804A1

公开(公告)日：2023-11-09

申请号：US18105815

申请日：2023-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYONGMO MOON ,  Taeryeong KIM ,  Seongook JUNG ,  Jeonghyeok YOU

IPC: H04B1/40 ,  H03K19/20 ,  H03K3/037 ,  H03K5/14 ,  H03K5/24

CPC classification number: H04B1/40 ,  H03K19/20 ,  H03K3/037 ,  H03K5/14 ,  H03K5/2472 ,  H03K2005/00078

Abstract: A transmitter circuit of an interface circuit includes a clock generating circuit, a pulse generating circuit, an overlapped multiplexing circuit, and an output circuit. The clock generating circuit generates a plurality of clocks having different phases. The pulse generating circuit generates a plurality of pulses based on the plurality of clocks. The overlapped multiplexing circuit receives a plurality of input signals in parallel, and sequentially outputs a plurality of overlapped signals based on the plurality of clocks, the plurality of input signals, and the plurality of pulses, and each overlapped signal includes bit values of two input signals among the plurality of input signals. The output circuit serially outputs bit values of the plurality of input signals in series based on the plurality of overlapped signal.

公开(公告)号：US20210225423A1

公开(公告)日：2021-07-22

申请号：US17143619

申请日：2021-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYONGMO MOON ,  SUNGOH AHN

IPC: G11C11/4074 ,  H01L25/18 ,  H01L23/00 ,  G11C11/4093 ,  G11C11/4096 ,  G06F1/10 ,  G06F1/26

Abstract: Disclosed is a memory device, which includes a buffer die that outputs a first power supply voltage to a first through-substrate via (e.g., through-silicon via (TSV)) and receives a small swing data signal from a second TSV generated based on the first power supply voltage, and a core die that is electrically connected to the buffer die through the first and second TSVs, includes a first cell capacitor electrically connected to the first TSV and configured to block a first noise introduced to the first power supply voltage received through the first TSV. The core die outputs the small swing data signal to the second TSV.

公开(公告)号：US20240146498A1

公开(公告)日：2024-05-02

申请号：US18197079

申请日：2023-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYONGMO MOON ,  Jeonghyeok YOU ,  Seongook JUNG ,  Taeryeong KIM ,  Hohyun Chae

IPC: H04L7/00 ,  G06F1/04 ,  H03K3/017 ,  H03K3/037 ,  H03K5/14

CPC classification number: H04L7/0016 ,  G06F1/04 ,  H03K3/017 ,  H03K3/037 ,  H03K5/14 ,  H03K19/20

Abstract: An apparatus for correcting an error of a clock signal may include a phase adjuster that corrects an error of half-rate clock signals based on an error correction signal to output an error-corrected clock signal, a phase splitter that outputs quadrature clock signals from the error-corrected clock signal, an error detector that outputs an internal clock signal based on one of the quadrature clock signals, selects two quadrature clock signals among the quadrature clock signals based on a clock selection signal, and detects errors of the two quadrature clock signals based on an error check signal to output a correction request signal, and a controller that outputs a mode selection signal and the clock selection signal based on the internal clock signal and that outputs the error correction signal and the error check signal based on the mode selection signal, the clock selection signal, and the correction request signal.

公开(公告)号：US20150023112A1

公开(公告)日：2015-01-22

申请号：US14248447

申请日：2014-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon-Joo EOM ,  BYONGMO MOON ,  YONGCHEOL BAE

IPC: H03K19/00 ,  G11C7/10

CPC classification number: G11C7/1084 ,  G11C7/1057 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/105 ,  G11C2207/2272 ,  H03K19/0005

Abstract: An integrated circuit includes a data input such as a data pad for receiving an external data signal input and an on-die termination (ODT) information input for receiving ODT information from an external device. An ODT circuit selectively couples a termination resistor to the data pad based on the ODT information. An input buffer is coupled to the data pad for determining data that is input into the pad using a reference voltage. A reference voltage generator is coupled to the input buffer and generates the reference voltage on the basis of the ODT information.

Abstract translation: 集成电路包括诸如用于接收外部数据信号输入的数据焊盘和输入的用于从外部设备接收ODT信息的芯片上端接（ODT）信息的数据输入。 ODT电路基于ODT信息将终端电阻选择性地耦合到数据焊盘。 输入缓冲器耦合到数据焊盘，用于使用参考电压确定输入到焊盘的数据。 参考电压发生器耦合到输入缓冲器，并基于ODT信息产生参考电压。