公开(公告)号：US09871144B2

公开(公告)日：2018-01-16

申请号：US15357273

申请日：2016-11-21

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Bong-Kyun Kim ,  Seung-Ho Yoon ,  Shin-Il Choi

IPC: H01L29/786 ,  H01L29/417 ,  H01L27/12 ,  H01L29/66 ,  H01L23/532 ,  H01L21/465 ,  H01L21/4763 ,  H01L21/441 ,  H01L29/45

CPC classification number: H01L29/7869 ,  H01L21/441 ,  H01L21/465 ,  H01L21/47635 ,  H01L23/53228 ,  H01L23/53238 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A thin film transistor substrate includes a gate electrode disposed on a substrate; a semiconductor layer disposed on the substrate that partially overlaps the gate electrode and includes an oxide semiconductor material; and a source electrode and a drain electrode disposed on the semiconductor layer, where the drain electrode is spaced apart from the source electrode. The source electrode and the drain electrode each include a barrier layer and a main wiring layer, the a main wiring layer is disposed on the barrier layer, and the barrier layer includes a first metal layer disposed on the semiconductor layer, and a second metal layer disposed on the first metal layer.

公开(公告)号：US09490275B2

公开(公告)日：2016-11-08

申请号：US14740484

申请日：2015-06-16

Applicant: Samsung Display Co., Ltd.

Inventor： Young Min Moon ,  Jong-Hyun Choung ,  Bong-Kyun Kim

IPC: H01L27/00 ,  H01L29/00 ,  H01L27/12 ,  H01L29/51 ,  H01L29/49 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/42356 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/7869

Abstract: A thin film transistor array panel includes: a gate line on a substrate and including a gate electrode; a first gate insulating layer on the substrate and the gate line, the first gate insulting layer including a first portion adjacent to the gate line and a second portion overlapping the gate line and having a smaller thickness than that of the first portion; a second gate insulating layer on the first gate insulating layer; a semiconductor layer on the second gate insulating layer; a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; a passivation layer on the second gate insulating layer, the source electrode and the drain electrode; and a pixel electrode on the passivation layer and connected with the drain electrode. The first gate insulating layer and the second gate insulating layer have stress in opposite directions from each other.

Abstract translation: 薄膜晶体管阵列面板包括：基板上的栅极线，并包括栅电极; 所述第一栅极绝缘层在所述基板和所述栅极线上，所述第一栅极绝缘层包括与所述栅极线相邻的第一部分和与所述栅极线重叠并且具有比所述第一部分的厚度小的第二部分; 第一栅极绝缘层上的第二栅极绝缘层; 在所述第二栅极绝缘层上的半导体层; 在半导体层上彼此隔开的源电极和漏电极; 第二栅极绝缘层上的钝化层，源电极和漏电极; 以及钝化层上的像素电极并与漏电极连接。 第一栅极绝缘层和第二栅极绝缘层在彼此相反的方向上具有应力。

公开(公告)号：US20130234124A1

公开(公告)日：2013-09-12

申请号：US13871368

申请日：2013-04-26

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： KAP-SOO YOON ,  Woo-Geun Lee ,  Bong-Kyun Kim ,  Sung-Hoon Yang ,  Ki-Won Kim ,  Hyun-Jung Lee

IPC: H01L29/786 ,  H01L51/52

CPC classification number: H01L29/78693 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L27/3248 ,  H01L27/3262 ,  H01L51/5203

Abstract: Provided are a thin-film transistor (TFT) substrate, a method of manufacturing the same, and a display device including the same. The TFT substrate includes a gate electrode formed on a substrate, a gate insulating layer formed on the gate electrode, an oxide semiconductor pattern formed on the gate insulating layer, a source electrode formed on the oxide semiconductor pattern, a drain electrode formed on the oxide semiconductor pattern to face the source electrode, and a pixel electrode formed on the gate insulating layer.

Abstract translation: 提供了一种薄膜晶体管（TFT）基板，其制造方法和包括该薄膜晶体管的显示装置。 TFT基板包括形成在基板上的栅电极，形成在栅电极上的栅极绝缘层，形成在栅极绝缘层上的氧化物半导体图案，形成在氧化物半导体图案上的源电极，形成在氧化物上的漏电极 面对源电极的半导体图案，以及形成在栅极绝缘层上的像素电极。

公开(公告)号：US10535510B2

公开(公告)日：2020-01-14

申请号：US14809028

申请日：2015-07-24

Applicant: Samsung Display Co., Ltd.

Inventor： Bong-Kyun Kim ,  Young-Min Moon ,  Soo-Min An

IPC: H01L21/02

Abstract: A substrate-treating apparatus includes a liquid-providing part, a first liquid-removing knife and a returning part. The liquid-providing part provides a first liquid chemical for cleaning a substrate that includes a metal pattern and a photoresist pattern on the metal pattern, and for removing an etchant that remains on the substrate. The first liquid-removing knife sprays a second liquid chemical in a direction inclined and opposite to a returning direction of the substrate, so as to remove the first liquid chemical, the first liquid chemical including a metal precipitate. The returning part returns the substrate from the liquid-providing part toward the first liquid-removing knife in the returning direction.

公开(公告)号：US09502579B2

公开(公告)日：2016-11-22

申请号：US14717734

申请日：2015-05-20

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Bong-Kyun Kim ,  Seung-Ho Yoon ,  Shin-Il Choi

IPC: H01L29/12 ,  H01L29/786 ,  H01L29/417 ,  H01L27/12 ,  H01L23/532 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/441 ,  H01L21/465 ,  H01L21/47635 ,  H01L23/53228 ,  H01L23/53238 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A thin film transistor substrate includes a gate electrode disposed on a substrate; a semiconductor layer disposed on the substrate that partially overlaps the gate electrode and includes an oxide semiconductor material; and a source electrode and a drain electrode disposed on the semiconductor layer, where the drain electrode is spaced apart from the source electrode. The source electrode and the drain electrode each include a barrier layer and a main wiring layer, the a main wiring layer is disposed on the barrier layer, and the barrier layer includes a first metal layer disposed on the semiconductor layer, and a second metal layer disposed on the first metal layer.

Abstract translation: 薄膜晶体管基板包括设置在基板上的栅电极; 半导体层，其设置在与所述栅电极部分重叠并且包括氧化物半导体材料的所述基板上; 以及设置在半导体层上的源电极和漏电极，其中漏电极与源电极间隔开。 源电极和漏极各自包括阻挡层和主布线层，主布线层设置在阻挡层上，阻挡层包括设置在半导体层上的第一金属层和第二金属层 设置在第一金属层上。

公开(公告)号：US09837550B2

公开(公告)日：2017-12-05

申请号：US15335897

申请日：2016-10-27

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Bong-Kyun Kim ,  Seung-Ho Yoon ,  Shin-Il Choi

IPC: H01L29/12 ,  H01L29/786 ,  H01L29/417 ,  H01L27/12 ,  H01L29/66 ,  H01L23/532 ,  H01L21/465 ,  H01L21/4763 ,  H01L21/441 ,  H01L29/45

CPC classification number: H01L29/7869 ,  H01L21/441 ,  H01L21/465 ,  H01L21/47635 ,  H01L23/53228 ,  H01L23/53238 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A thin film transistor substrate includes a gate electrode disposed on a substrate; a semiconductor layer disposed on the substrate that partially overlaps the gate electrode and includes an oxide semiconductor material; and a source electrode and a drain electrode disposed on the semiconductor layer, where the drain electrode is spaced apart from the source electrode. The source electrode and the drain electrode each include a barrier layer and a main wiring layer, the a main wiring layer is disposed on the barrier layer, and the barrier layer includes a first metal layer disposed on the semiconductor layer, and a second metal layer disposed on the first metal layer.

公开(公告)号：US09443881B2

公开(公告)日：2016-09-13

申请号：US14518278

申请日：2014-10-20

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jean-Ho Song ,  Shin-Il Choi ,  Sun-Young Hong ,  Shi-Yul Kim ,  Ki-Yeup Lee ,  Jae-Hyoung Youn ,  Sung-Ryul Kim ,  O-Sung Seo ,  Yang-Ho Bae ,  Jong-Hyun Choung ,  Dong-Ju Yang ,  Bong-Kyun Kim ,  Hwa-Yeul Oh ,  Pil-Soon Hong ,  Byeong-Beom Kim ,  Je-Hyeong Park ,  Yu-Gwang Jeong ,  Jong-In Kim ,  Nam-Seok Suh

IPC: H01L29/04 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1288 ,  H01L29/42368 ,  H01L29/458 ,  H01L29/78669

Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.

Abstract translation: 薄膜晶体管阵列面板包括栅极线，覆盖栅极线的栅极绝缘层，设置在栅极绝缘层上的半导体层，设置在半导体层上的数据线和漏极，钝化层 覆盖数据线和漏电极，并且具有露出漏电极的一部分的接触孔，以及通过接触孔与漏电极电连接的像素电极。 数据线和漏极各自具有包括钛的下层和铜的上层的双层，下层比上层宽，下层具有暴露的区域。 栅极绝缘层可以具有台阶形状。

公开(公告)号：US09305940B2

公开(公告)日：2016-04-05

申请号：US14463574

申请日：2014-08-19

Applicant: Samsung Display Co., LTD.

Inventor： Bong-Kyun Kim ,  Young-Min Moon

IPC: H01L29/10 ,  H01L29/04 ,  H01L29/12 ,  H01L21/00 ,  H01L27/12 ,  H01L29/45 ,  H01L21/441 ,  H01L21/465 ,  H01L21/467 ,  H01L21/768 ,  H01L21/3213 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01L27/1225 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/32134 ,  H01L21/441 ,  H01L21/465 ,  H01L21/467 ,  H01L21/76846 ,  H01L27/1259 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/78618 ,  H01L29/7869

Abstract: A thin film transistor includes a gate electrode, an active pattern overlapping with the gate electrode and including a semiconductive oxide, and a source metal pattern disposed on the active pattern and including a source electrode and a drain electrode spaced apart from the source electrode. The active pattern underlaps an entire portion of a lower surface of the source metal pattern and minimally protrudes beyond lateral ends of the source metal pattern due to the active pattern having sidewall taper angles that are substantially greater than corresponding and adjacent sidewall taper angles of the overlying source metal pattern. Thus parasitic capacitance may be reduced and performance enhanced.

Abstract translation: 薄膜晶体管包括栅电极，与栅电极重叠并且包括半导体氧化物的有源图案，以及设置在有源图案上的源极金属图案，并且包括与源电极间隔开的源电极和漏电极。 活性图案使得源金属图案的下表面的整个部分下垂，并且由于活性图案具有基本上大于上覆的相应和相邻侧壁锥角的侧壁锥角而最小地突出超过源金属图案的横向端部 源金属图案。 因此，可以降低寄生电容并提高性能。

公开(公告)号：US20150053984A1

公开(公告)日：2015-02-26

申请号：US14518278

申请日：2014-10-20

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： JEAN-HO SONG ,  Shin-Il Choi ,  Sun-Young Hong ,  Shi-Yul Kim ,  Ki-Yeup Lee ,  Jae-Hyoung Youn ,  Sung-Ryul Kim ,  O-Sung Seo ,  Yang-Ho Bae ,  Jong-Hyun Choung ,  Dong-Ju Yang ,  Bong-Kyun Kim ,  Hwa-Yeul Oh ,  Pil-Soon Hong ,  Byeong-Beom Kim ,  Je-Hyeong Park ,  Yu-Gwang Jeong ,  Jong-In Kim ,  Nam-Seok Suh

IPC: H01L27/12 ,  H01L29/45 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1288 ,  H01L29/42368 ,  H01L29/458 ,  H01L29/78669

Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.

Abstract translation: 薄膜晶体管阵列面板包括栅极线，覆盖栅极线的栅极绝缘层，设置在栅极绝缘层上的半导体层，设置在半导体层上的数据线和漏极，钝化层 覆盖数据线和漏电极，并且具有露出漏电极的一部分的接触孔，以及通过接触孔与漏电极电连接的像素电极。 数据线和漏极各自具有包括钛的下层和铜的上层的双层，下层比上层宽，下层具有暴露的区域。 栅极绝缘层可以具有台阶形状。