Method for manufacturing thin film transistor array panel
    1.
    发明授权
    Method for manufacturing thin film transistor array panel 有权
    制造薄膜晶体管阵列面板的方法

    公开(公告)号:US09490275B2

    公开(公告)日:2016-11-08

    申请号:US14740484

    申请日:2015-06-16

    CPC classification number: H01L29/42356 H01L29/42384 H01L29/4908 H01L29/7869

    Abstract: A thin film transistor array panel includes: a gate line on a substrate and including a gate electrode; a first gate insulating layer on the substrate and the gate line, the first gate insulting layer including a first portion adjacent to the gate line and a second portion overlapping the gate line and having a smaller thickness than that of the first portion; a second gate insulating layer on the first gate insulating layer; a semiconductor layer on the second gate insulating layer; a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; a passivation layer on the second gate insulating layer, the source electrode and the drain electrode; and a pixel electrode on the passivation layer and connected with the drain electrode. The first gate insulating layer and the second gate insulating layer have stress in opposite directions from each other.

    Abstract translation: 薄膜晶体管阵列面板包括:基板上的栅极线,并包括栅电极; 所述第一栅极绝缘层在所述基板和所述栅极线上,所述第一栅极绝缘层包括与所述栅极线相邻的第一部分和与所述栅极线重叠并且具有比所述第一部分的厚度小的第二部分; 第一栅极绝缘层上的第二栅极绝缘层; 在所述第二栅极绝缘层上的半导体层; 在半导体层上彼此隔开的源电极和漏电极; 第二栅极绝缘层上的钝化层,源电极和漏电极; 以及钝化层上的像素电极并与漏电极连接。 第一栅极绝缘层和第二栅极绝缘层在彼此相反的方向上具有应力。

Patent Agency Ranking