公开(公告)号：US09960090B2

公开(公告)日：2018-05-01

申请号：US15476189

申请日：2017-03-31

Applicant: Samsung Display Co., LTD.

Inventor： Ji-Yun Hong ,  Joon-Geol Kim ,  Jin-Won Lee ,  Ki-Won Kim

IPC: H01L21/66 ,  H01L27/12 ,  G09G3/00

CPC classification number: H01L22/32 ,  G09G3/006 ,  H01L22/14 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1259

Abstract: A display panel includes first and second test lines connected to the each of data lines, extending in the second direction, and arranged in the first direction, a first test pad electrically connected to the first test line, the first test pad and the first test line being formed from a same layer, and a second test pad electrically connected to the second test line through a contact hole formed through a first insulation layer and disposed adjacent to the first test pad in the second direction.

公开(公告)号：US09633916B2

公开(公告)日：2017-04-25

申请号：US14458152

申请日：2014-08-12

Applicant: Samsung Display Co., LTD.

Inventor： Ji-Yun Hong ,  Joon-Geol Kim ,  Jin-Won Lee ,  Ki-Won Kim

IPC: H01L21/66 ,  H01L27/12 ,  G09G3/00

CPC classification number: H01L22/32 ,  G09G3/006 ,  H01L22/14 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1259

Abstract: A display panel includes first to third test lines connected to the each of data lines, extending in the second direction, and arranged in the first direction, a first test pad electrically connected to the first test line, the first test pad and the first test line being formed from a same layer, a second test pad electrically connected to the second test line through a contact hole formed through a first insulation layer, and disposed adjacent to the first test pad in the second direction, a third test pad electrically connected to the third test line and disposed adjacent to the first test pad in the first direction, the third test pad and the third test line being formed from a same layer.

公开(公告)号：US09443877B2

公开(公告)日：2016-09-13

申请号：US14799060

申请日：2015-07-14

Applicant: Samsung Display Co., Ltd.

Inventor： Pil-Sang Yun ,  Ki-Won Kim ,  Hye-Young Ryu ,  Woo-Geun Lee ,  Seung-Ha Choi ,  Jae-Hyoung Youn ,  Kyoung-Jae Chung ,  Young-Wook Lee ,  Je-Hun Lee ,  Kap-Soo Yoon ,  Do-Hyun Kim ,  Dong-Ju Yang ,  Young-Joo Choi

IPC: H01L29/04 ,  H01L31/036 ,  H01L27/12 ,  H01L21/4757 ,  H01L21/441 ,  H01L21/475 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/41733 ,  H01L21/44 ,  H01L21/441 ,  H01L21/465 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

公开(公告)号：US11804495B2

公开(公告)日：2023-10-31

申请号：US17886489

申请日：2022-08-12

Applicant: Samsung Display Co., Ltd.

Inventor： Young-Wook Lee ,  Woo-Geun Lee ,  Ki-Won Kim ,  Hyun-Jung Lee ,  Ji-Soo Oh

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/768

CPC classification number: H01L27/124 ,  H01L21/76834 ,  H01L27/127 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1262 ,  H01L27/1288 ,  H01L29/78693 ,  H01L29/7869

Abstract: A substrate including a first signal line and a first electrode disposed on the substrate, an oxide semiconductor layer pattern overlapping the first electrode, an insulating layer disposed between the first electrode and the oxide semiconductor layer pattern, a second signal line intersecting the first signal line, a second electrode electrically connected to the oxide semiconductor layer pattern, a third electrode electrically connected to the oxide semiconductor layer pattern and spaced apart from the second electrode, and an insulator comprising a first portion disposed between the first signal line and the second signal line, and at least partially overlapping with both of the first signal line and the second signal line.

公开(公告)号：US11437412B2

公开(公告)日：2022-09-06

申请号：US17124497

申请日：2020-12-17

Applicant: Samsung Display Co., Ltd.

Inventor： Young-Wook Lee ,  Woo-Geun Lee ,  Ki-Won Kim ,  Hyun-Jung Lee ,  Ji-Soo Oh

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/768

Abstract: A substrate including a gate line and a first electrode disposed on the substrate, an oxide semiconductor layer pattern overlapping the first electrode, an insulating layer disposed between the first electrode and the oxide semiconductor layer pattern, a data line intersecting the gate line, a second electrode electrically connected to the oxide semiconductor layer pattern, a third electrode electrically connected to the oxide semiconductor layer, the third electrode spaced apart from the second electrode, and an insulating pattern including a first portion which is disposed between the gate line and the data line and at least partially overlaps with both of the gate line and the data line.

公开(公告)号：US20150318312A1

公开(公告)日：2015-11-05

申请号：US14799060

申请日：2015-07-14

Applicant: Samsung Display Co.,Ltd

Inventor： Pil-Sang Yun ,  Ki-Won Kim ,  Hye-Young Ryu ,  Woo-Geun Lee ,  Seung-Ha Choi ,  Jae-Hyoung Youn ,  Kyoung-Jae Chung ,  Young-Wook Lee ,  Je-Hun Lee ,  Kap-Soo Yoon ,  Do-Hyun Kim ,  Dong-Ju Yang ,  Young-Joo Choi

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/44 ,  H01L21/441 ,  H01L21/465 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

公开(公告)号：US08563368B2

公开(公告)日：2013-10-22

申请号：US13758716

申请日：2013-02-04

Applicant: Samsung Display Co., Ltd

Inventor： Young-Wook Lee ,  Hong-Suk Yoo ,  Jean-Ho Song ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Ki-Won Kim ,  Jong-In Kim

IPC: H01L21/00

CPC classification number: H01L29/66742 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248

Abstract: A thin film transistor substrate according to an embodiment of the present invention includes: an insulation substrate; a gate line formed on the insulation substrate; a first interlayer insulating layer formed on the gate line; a data line and a gate electrode formed on the first interlayer insulating layer; a gate insulating layer formed on the data line and gate electrode; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; a second interlayer insulating layer formed on the semiconductor; a first connection formed on the second interlayer insulating layer and electrically connecting the gate line and the gate electrode to each other; a drain electrode connected to the semiconductor; a pixel electrode connected to the drain electrode; and a second connection connecting the data line and the semiconductor to each other.

公开(公告)号：US20130248866A1

公开(公告)日：2013-09-26

申请号：US13897879

申请日：2013-05-20

Applicant: Samsung Display Co., Ltd.

Inventor： Young-Wook LEE ,  Woo-Geun Lee ,  Ki-Won Kim ,  Hyun-Jung Lee ,  Ji-Soo Oh

IPC: H01L29/786

CPC classification number: H01L27/124 ,  H01L21/76834 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1262 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/7869 ,  H01L29/78693

Abstract: A thin film transistor (TFT) array substrate and a manufacturing method thereof are provided. The TFT array substrate may include a gate line disposed on a substrate and including a gate line and a gate electrode, an oxide semiconductor layer pattern disposed on the gate electrode, a data line disposed on the oxide semiconductor layer pattern and including a source electrode and a drain electrode of a thin film transistor (TFT) together with the gate electrode, and a data line extending in a direction intersecting the gate line, and etch stop patterns disposed at an area where the TFT is formed between the source/drain electrodes and the oxide semiconductor layer pattern and at an area where the gate line and the data line overlap each other between the gate line and the data line.

Abstract translation: 提供薄膜晶体管（TFT）阵列基板及其制造方法。 TFT阵列基板可以包括设置在基板上的栅极线，包括栅极线和栅电极，设置在栅电极上的氧化物半导体层图案，设置在氧化物半导体层图案上的数据线，并且包括源电极和 薄膜晶体管（TFT）的漏电极和栅电极以及沿着与栅极线交叉的方向延伸的数据线，以及蚀刻停止图案，设置在源极/漏极之间形成TFT的区域，以及 氧化物半导体层图案和栅极线与数据线在栅极线与数据线之间重叠的区域。

公开(公告)号：US10355025B2

公开(公告)日：2019-07-16

申请号：US15813758

申请日：2017-11-15

Applicant: Samsung Display Co., Ltd.

Inventor： Young-Wook Lee ,  Woo-Geun Lee ,  Ki-Won Kim ,  Hyun-Jung Lee ,  Ji-Soo Oh

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/768

Abstract: A substrate including gate wirings including a gate line and a gate electrode disposed on a substrate, an oxide semiconductor layer pattern overlapping the gate electrode, a gate insulating layer disposed between the gate wirings and the oxide semiconductor layer pattern, data wirings including a data line crossing the gate line, a source electrode connected to one side of the oxide semiconductor layer pattern, and a drain electrode connected to another side of the oxide semiconductor layer, and an insulating pattern including a first portion which is disposed between the gate line and the data line and at least partially overlaps with both of the gate line and the data line.

公开(公告)号：US09520419B2

公开(公告)日：2016-12-13

申请号：US14793183

申请日：2015-07-07

Applicant: Samsung Display Co., Ltd.

Inventor： Young-Wook Lee ,  Woo-Geun Lee ,  Ki-Won Kim ,  Hyun-Jung Lee ,  Ji-Soo Oh

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L21/76834 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1262 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/7869 ,  H01L29/78693

Abstract: A method of manufacturing a thin film transistor (TFT) array substrate includes forming a gate line and a gate electrode on a substrate, forming a gate-insulating layer and an oxide semiconductor layer on the gate line and the gate electrode, forming etch stop patterns at a thin-film transistor area and an area where the gate line and the data line overlap each other, forming a data conductor on the oxide semiconductor layer and the etch stop patterns, the data conductor comprising a source electrode and a drain electrode that constitute a TFT together with the gate electrode, and forming a data line extending in a direction intersecting the gate line.

Abstract translation: 制造薄膜晶体管（TFT）阵列基板的方法包括在基板上形成栅极线和栅电极，在栅极线和栅电极上形成栅极绝缘层和氧化物半导体层，形成蚀刻停止图案 在薄膜晶体管区域和栅极线和数据线彼此重叠的区域中，在氧化物半导体层和蚀刻停止图案上形成数据导体，数据导体包括源电极和漏极，构成 TFT与栅极电极一起形成，并且在与栅极线相交的方向上形成数据线。