知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

37 records (took 0.021 seconds)

    Semiconductor device
    13.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11508751B2

    公开(公告)日：2022-11-22

    申请号：US17144458

    申请日：2021-01-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Namkyu Edward Cho ,  Seok Hoon Kim ,  Myung Il Kang ,  Geo Myung Shin ,  Seung Hun Lee ,  Jeong Yun Lee ,  Min Hee Choi ,  Jeong Min Choi

    IPC: H01L29/66 ,  H01L29/78 ,  H01L27/11582 ,  H01L21/768

    Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.

    WET ETCHING APPARATUS
    16.
    发明申请
    WET ETCHING APPARATUS 审中-公开

    公开(公告)号：US20200075359A1

    公开(公告)日：2020-03-05

    申请号：US16376749

    申请日：2019-04-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JIN WOO LEE ,  Yong Jun Choi ,  Seok Hoon Kim ,  Seung Min Shin ,  Ji Hoon Cha

    IPC: H01L21/67

    Abstract: A wet etching apparatus includes a process bath having an internal space configured to receive an etchant and having a support unit, on which a wafer is disposed to be in contact with the etchant. A laser unit is disposed above the process bath and is configured to direct a laser beam to the wafer and to heat the wafer thereby. An etchant supply unit is configured to supply the etchant to the internal space of the process bath.

    Graphics processing unit and device employing tessellation decision
    17.
    发明授权
    Graphics processing unit and device employing tessellation decision 有权

    公开(公告)号：US10140677B2

    公开(公告)日：2018-11-27

    申请号：US14823476

    申请日：2015-08-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seok Hoon Kim ,  Chang Hyo Yu

    IPC: G06T1/20 ,  G06T17/20 ,  G06T1/60

    Abstract: A graphics processing unit (GPU) for determining whether to perform tessellation on a first model according to a control of a central processing unit (CPU) is provided. The GPU reads the first model from a memory, which stores prepared models having different complexities; calculates a complexity of the first model; compares the calculated complexity with a reference complexity; and determines whether to perform a tessellation operation on the first model according to a comparison result.

    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THEREOF
    19.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THEREOF 审中-公开

    公开(公告)号：US20230253449A1

    公开(公告)日：2023-08-10

    申请号：US17935528

    申请日：2022-09-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dong Suk Shin ,  Hyun-Kwan Yu ,  Seok Hoon Kim ,  Pan Kwi Park ,  Yong Seung Kim ,  Jung Taek Kim

    IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/762

    CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L29/4232 ,  H01L29/66553

    Abstract: A semiconductor device includes a lower pattern extending in a first direction and sheet patterns spaced apart therefrom in a second direction, a gate structure on the lower pattern and including a gate insulating layer, a gate spacer, and a gate electrode, a source/drain pattern on the lower pattern and in contact with the sheet patterns and the gate insulating layer, and a first etch blocking pattern between the gate spacer and the source/drain pattern. The gate spacer includes an inner sidewall extending in the third direction, and a connection sidewall extending from the inner sidewall in the first direction. The source/drain pattern includes a semiconductor filling layer on a semiconductor liner layer that is in contact with the sheet pattern and includes a facet surface extending from the connection sidewall. The first etch blocking pattern is in contact with the facet surface and the connection sidewall.

Patent Agency Ranking