公开(公告)号：US20230253498A1

公开(公告)日：2023-08-10

申请号：US18303288

申请日：2023-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunseong LEE ,  Jinseong HEO ,  Sangwook KIM ,  Taewan MOON ,  Sanghyun JO

IPC: H01L29/78 ,  H01L29/51 ,  H10B51/30

CPC classification number: H01L29/78391 ,  H01L29/516 ,  H10B51/30 ,  H01L21/02181

Abstract: Provided is a ferroelectric thin-film structure including a semiconductor substrate, a first ferroelectric layer on the semiconductor substrate, and a second ferroelectric layer on the semiconductor substrate. The second ferroelectric layer is spaced apart from the first ferroelectric layer and has a different dielectric constant from the first ferroelectric layer. The first ferroelectric layer and the second ferroelectric layer may be different from each other in terms of the amount of a dopant contained therein, and may exhibit different threshold voltages when applied to transistors.

公开(公告)号：US20230238460A1

公开(公告)日：2023-07-27

申请号：US18158176

申请日：2023-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwook KIM ,  Kyung-Eun Byun ,  Keunwook Shin ,  Moonil Jung ,  Euntae Kim ,  Jeeeun Yang ,  Kwanghee Lee

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/16

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/1606

Abstract: A transistor includes an oxide semiconductor layer, a source electrode and a drain electrode disposed spaced apart from each other on the oxide semiconductor layer, a gate electrode spaced apart from the oxide semiconductor layer, a gate insulating layer disposed between the oxide semiconductor layer and the gate electrode, and a graphene layer disposed between the gate electrode and the gate insulating layer and doped with a metal.

公开(公告)号：US20230176469A1

公开(公告)日：2023-06-08

申请号：US17812005

申请日：2022-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heungsuk OH ,  Kyu-Bin HAN ,  Sangwook KIM

IPC: G03F1/36 ,  H01L21/768 ,  H01L21/027

CPC classification number: G03F1/36 ,  H01L21/768 ,  H01L21/027

Abstract: Provided is a method of fabricating a semiconductor device using a curvilinear OPC method. The method of fabricating the semiconductor device includes performing an optical proximity correction (OPC) step on a layout to generate a correction pattern, the correction pattern having a curvilinear shape, performing a mask rule check (MRC) step on the correction pattern to generate mask data, and forming a photoresist pattern on a substrate using a photomask, which is manufactured based on the mask data. The MRC step includes generating a width skeleton in the correction pattern, generating a width contour, which satisfies a specification of a mask rule for a linewidth, from the width skeleton, and adding the correction pattern and the width contour to generate an adjusting pattern.

公开(公告)号：US20210367080A1

公开(公告)日：2021-11-25

申请号：US17308543

申请日：2021-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanghee LEE ,  Sangwook KIM ,  Jinseong HEO

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66

Abstract: An oxide semiconductor transistor includes: an insulating substrate including a trench; a gate electrode in the trench; an oxide semiconductor layer on a surface of the insulating substrate, the surface exposed through the trench; and a ferroelectric layer between the gate electrode and the oxide semiconductor layer, wherein the oxide semiconductor layer may include a source region and a drain region which are on the insulating substrate outside the trench and are apart from each other with the gate electrode therebetween.

公开(公告)号：US20210091227A1

公开(公告)日：2021-03-25

申请号：US17026665

申请日：2020-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Sangwook KIM ,  Yunseong LEE ,  Sanghyun JO

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  G11C11/22

Abstract: A domain switching device includes a channel region, a source region and a drain region connected to the channel region, a gate electrode isolated from contact with the channel region, an anti-ferroelectric layer between the channel region and the gate electrode, a conductive layer between the gate electrode and the anti-ferroelectric layer to contact the anti-ferroelectric layer, and a barrier layer between the anti-ferroelectric layer and the channel region.

公开(公告)号：US20210083121A1

公开(公告)日：2021-03-18

申请号：US17001979

申请日：2020-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Sangwook KIM ,  Yunseong LEE ,  Sanghyun JO ,  Hyangsook LEE

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/40

Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device includes a ferroelectric crystallization layer between a substrate and a gate electrode and a crystallization prevention layer between the substrate and the ferroelectric crystallization layer. The ferroelectric crystallization layer is at least partially crystallized and includes a dielectric material having ferroelectricity or anti-ferroelectricity. Also, the crystallization prevention layer prevents crystallization in the ferroelectric crystallization layer from being spread toward the substrate.

公开(公告)号：US20190369457A1

公开(公告)日：2019-12-05

申请号：US16134614

申请日：2018-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghyun PARK ,  Sangwook KIM ,  Sunil KIM

IPC: G02F1/19 ,  G02F1/01 ,  G02F1/1343 ,  G02B5/00

Abstract: An optical modulation device and an apparatus including the same are provided. The optical modulation device may include a reflector, a nano-antenna array placed opposite to the reflector, and an active layer that is placed between the reflector and the nano-antenna array. The optical modulation device may further include a first insulating layer placed between the reflector and the active layer, a second insulating layer placed between the active layer and the nano-antenna array, and a wiring structure that electrically contacts the active layer. The wiring structure may be provided in at least one of a first place between the active layer and the first insulating layer and a second place between the active layer and the second insulating layer.

公开(公告)号：US20150243402A1

公开(公告)日：2015-08-27

申请号：US14556344

申请日：2014-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  AJOU UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION

Inventor： Kyungsang CHO ,  Sangwook KIM ,  Donghyeok CHOI

IPC: H01B1/06 ,  B05D3/00 ,  B05D7/00 ,  B05D1/38

CPC classification number: H01B1/06 ,  B01J13/02 ,  B82Y30/00 ,  C03C17/347 ,  C03C17/3476 ,  C03C2218/31 ,  H01B1/10

Abstract: A nanoparticle multilayer thin film is provided in which nanoparticles which are not electrically insulated from each other are spaced apart from one another at a reduced distance. The nanoparticle multilayer film includes: at least one first nanoparticle layer including first nanoparticles that are surface-modified with a cationic metal-chalcogenide compound; and at least one second nanoparticle layer including second nanoparticles that are surface-modified with an anionic metal-chalcogenide compound, wherein the first nanoparticle layer and the second nanoparticle layer are alternately stacked upon one another.

Abstract translation: 提供了纳米颗粒多层薄膜，其中彼此不电绝缘的纳米颗粒彼此间隔距离缩小。 纳米颗粒多层膜包括：至少一个第一纳米颗粒层，其包括用阳离子金属 - 硫属化合物化合物进行表面改性的第一纳米颗粒; 以及包含用阴离子金属 - 硫属化合物表面改性的第二纳米颗粒的至少一个第二纳米颗粒层，其中所述第一纳米颗粒层和所述第二纳米颗粒层彼此交替堆叠。

公开(公告)号：US20250006844A1

公开(公告)日：2025-01-02

申请号：US18756169

申请日：2024-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeeeun YANG ,  Sangwook KIM ,  Youngkwan CHA

IPC: H01L29/786 ,  H01L27/118 ,  H01L29/66 ,  H10B10/00

Abstract: A semiconductor device includes an oxide semiconductor layer, a first electrode and a second electrode, which are arranged apart from each other on the oxide semiconductor layer, a metal oxide layer arranged between the oxide semiconductor layer and at least one of the first electrode and the second electrode, and a metal nitride layer arranged between the metal oxide layer and the oxide semiconductor layer.

公开(公告)号：US20240266445A1

公开(公告)日：2024-08-08

申请号：US18638923

申请日：2024-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Taehwan MOON ,  Hagyoul BAE ,  Seunggeol NAM ,  Sangwook KIM ,  Kwanghee LEE

IPC: H01L29/86 ,  H10B69/00 ,  H10K10/50 ,  H10K19/00

CPC classification number: H01L29/86 ,  H10B69/00 ,  H10K10/50 ,  H10K19/00 ,  H10K19/201

Abstract: A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.