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    OPTICAL PROXIMITY CORRECTION METHODS AND MASK MANUFACTURING METHODS INCLUDING THE OPTICAL PROXIMITY CORRECTION METHODS
    1.
    发明申请
    OPTICAL PROXIMITY CORRECTION METHODS AND MASK MANUFACTURING METHODS INCLUDING THE OPTICAL PROXIMITY CORRECTION METHODS 有权

    公开(公告)号：US20250028235A1

    公开(公告)日：2025-01-23

    申请号：US18643392

    申请日：2024-04-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Heungsuk OH ,  Hun KANG ,  Sangwook KIM ,  Sanghun KIM ,  Sujin OH ,  Jinseok OH

    IPC: G03F1/36 ,  G03F1/70 ,  G06F30/392 ,  G06F119/18

    Abstract: Provided are an optical proximity correction (OPC) method capable of maintaining full-chip bias consistency and a mask manufacturing method including the OPC method. The OPC method includes obtaining a first optical proximity corrected (OPCed) design layout by implementing a first OPC on an OPC target design layout; performing a reverse dissection on the OPC target design layout based on the first OPCed design layout to generate first segments; performing a reverse correction to allocate first biases of the first OPCed design layout to the first segments of the OPC target design layout; determining a full-chip representative bias based on a segment grouping of the first segments; applying the full-chip representative bias to an entire chip area; preparing mask data based on the full-chip representative bias that has been applied to the entire chip area; and exposing a mask substrate based on the mask data.

    ELECTRONIC DEVICE FOR MANUFACTURING SEMICONDUCTOR DEVICE AND OPERATING METHOD OF ELECTRONIC DEVICE
    5.
    发明申请
    ELECTRONIC DEVICE FOR MANUFACTURING SEMICONDUCTOR DEVICE AND OPERATING METHOD OF ELECTRONIC DEVICE 有权

    公开(公告)号：US20230028712A1

    公开(公告)日：2023-01-26

    申请号：US17701520

    申请日：2022-03-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sooyong LEE ,  Dongho KIM ,  Sangwook KIM ,  Jungmin KIM ,  Seunghune YANG ,  Jeeyong LEE ,  Changmook YIM ,  Yangwoo HEO

    IPC: G06F30/392 ,  G03F7/20

    Abstract: Disclosed is an operating method of an electronic device which includes receiving a design layout for manufacturing the semiconductor device, generating a first layout by performing machine learning-based process proximity correction (PPC), generating a second layout by performing optical proximity correction (OPC), and outputting the second layout for a semiconductor process. The generating of the first layout includes generating a first after cleaning inspection (ACI) layout by executing a machine learning-based process proximity correction module on the design layout, generating a second after cleaning inspection layout by adjusting the design layout based on a difference of the first after cleaning inspection layout and the design layout and executing the process proximity correction module on the adjusted layout, and outputting the adjusted layout as the first layout, when a difference between the second after cleaning inspection layout and the design layout is smaller than or equal to a threshold value.

    MEMORY DEVICE INCLUDING VERTICAL CHANNEL TRANSISTOR AND ELECTRONIC DEVICE INCLUDING THE SAME
    9.
    发明公开
    MEMORY DEVICE INCLUDING VERTICAL CHANNEL TRANSISTOR AND ELECTRONIC DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240215215A1

    公开(公告)日：2024-06-27

    申请号：US18534220

    申请日：2023-12-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sangwook KIM ,  Kwanghee LEE ,  Jeeeun YANG ,  Moonil JUNG ,  Euntae KIM ,  Youngkwan CHA

    IPC: H10B12/00

    CPC classification number: H10B12/00

    Abstract: A memory device includes a read word line on a substrate, a first channel extending along a plane perpendicular to an upper surface of the substrate, a second channel facing the first channel in parallel, a first gate insulation layer adjacent to the first channel between the first channel and the second channel, a second gate insulation layer adjacent to the second channel between the first channel and the second channel, a gate electrode adjacent to the first gate insulation layer between the first gate insulation layer and the second gate insulation layer, a write word line adjacent to the second gate insulation layer between the first gate insulation layer and the second gate insulation layer, a read bit line electrically connected to the first channel, and a write bit line electrically connected to the second channel.

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