公开(公告)号：US20150110383A1

公开(公告)日：2015-04-23

申请号：US14340910

申请日：2014-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiho YANG ,  Seunghune YANG ,  Sibo CAI

IPC: G06T7/00 ,  G06T11/60 ,  G06K9/46

CPC classification number: G01N21/956 ,  G01N21/88 ,  G01N21/8851 ,  G03F7/70616 ,  G06K9/4604 ,  G06T7/0006 ,  G06T7/001 ,  G06T11/60 ,  G06T2207/20221 ,  G06T2207/30148

Abstract: Inventive concepts provide a method of inspecting a semiconductor device including obtaining inspection image data of an inspection pattern of an inspection layer on a substrate. The method may include extracting inspection contour data including an inspection pattern contour from the inspection image data, and merging the inspection contour data with comparison contour data of a comparison layer to obtain merged data. The comparison layer may overlap the inspection layer. The method may also include determining a horizontal distance between the inspection pattern contour and a comparison pattern contour of the comparison contour data based on the merged data.

Abstract translation: 本发明的概念提供了一种检查半导体器件的方法，包括获得在衬底上检查层的检查图案的检查图像数据。 该方法可以包括从检查图像数据提取包括检查图案轮廓的检查轮廓数据，并且将检查轮廓数据与比较层的比较轮廓数据合并以获得合并的数据。 比较层可以与检查层重叠。 该方法还可以包括基于合并的数据确定检查图案轮廓和比较轮廓数据的比较花样轮廓之间的水平距离。

公开(公告)号：US20230028712A1

公开(公告)日：2023-01-26

申请号：US17701520

申请日：2022-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooyong LEE ,  Dongho KIM ,  Sangwook KIM ,  Jungmin KIM ,  Seunghune YANG ,  Jeeyong LEE ,  Changmook YIM ,  Yangwoo HEO

IPC: G06F30/392 ,  G03F7/20

Abstract: Disclosed is an operating method of an electronic device which includes receiving a design layout for manufacturing the semiconductor device, generating a first layout by performing machine learning-based process proximity correction (PPC), generating a second layout by performing optical proximity correction (OPC), and outputting the second layout for a semiconductor process. The generating of the first layout includes generating a first after cleaning inspection (ACI) layout by executing a machine learning-based process proximity correction module on the design layout, generating a second after cleaning inspection layout by adjusting the design layout based on a difference of the first after cleaning inspection layout and the design layout and executing the process proximity correction module on the adjusted layout, and outputting the adjusted layout as the first layout, when a difference between the second after cleaning inspection layout and the design layout is smaller than or equal to a threshold value.

公开(公告)号：US20250138434A1

公开(公告)日：2025-05-01

申请号：US18806848

申请日：2024-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongchan CHO ,  Minjae KIM ,  Sungmin NAM ,  Seunghune YANG

IPC: G03F7/00

Abstract: Provided are a method of configuring an optimized extreme ultraviolet (EUV) illumination system, and an EUV exposure method using the EUV illumination system. The method of configuring the EUV illumination system includes calculating an aerial image by performing an optical simulation with respect to each of EUV point sources, summing up the aerial images based on EUV mapping, searching for a combination of the EUV point sources by using a fitness value with respect to the summed aerial image, and configuring the EUV illumination system as a combination of the EUV point sources, which has a maximum fitness value.

公开(公告)号：US20230194979A1

公开(公告)日：2023-06-22

申请号：US17938138

申请日：2022-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mijin KWON ,  Seunghune YANG ,  Youngyeop LEE

IPC: G03F1/70 ,  G03F1/36 ,  G06F30/398

CPC classification number: G03F1/70 ,  G03F1/36 ,  G06F30/398

Abstract: A method of correcting an error of a layout of a pattern includes: designing a layout of a target pattern; checking an error between the layout of the target pattern and a layout of a real pattern in a photomask manufactured based on the layout of the target pattern; generating EPE vectors at a plurality of points, respectively, in a contour of the layout of the target pattern;
calculating horizontal and vertical elements in horizontal and vertical directions, respectively, of each of the generated EPE vectors; calculating an offset representative value of the layout of the target pattern at each direction based on the calculated horizontal and vertical elements of the EPE vectors; and correcting the layout of the target pattern based on the offset representative value.

公开(公告)号：US20220382249A1

公开(公告)日：2022-12-01

申请号：US17566151

申请日：2021-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sooyong LEE ,  Mi-Jin KWON ,  Dongho KIM ,  Seunghune YANG

IPC: G05B19/4099

Abstract: A method for manufacturing a semiconductor device, includes receiving a first layout including patterns for the manufacturing of the semiconductor device, generating a second layout by performing machine learning-based process proximity correction (PPC) based on features of the patterns of the first layout, generating a third layout by performing optical proximity correction (OPC) on the second layout, and performing a multiple patterning process based on the third layout. The multiple patterning process includes patterning first-type patterns, and patterning second-type patterns. The machine learning-based process proximity correction is performed based on features of the first-type patterns and features of the second-type patterns.