公开(公告)号：US20240320412A1

公开(公告)日：2024-09-26

申请号：US18492206

申请日：2023-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooyong LEE

IPC: G06F30/398 ,  G06F30/392

CPC classification number: G06F30/398 ,  G06F30/392

Abstract: A deep learning-based process proximity correction method includes receiving a first layout associated with an After Cleaning Inspection (ACI), the first layout including a plurality of patterns associated with manufacturing a semiconductor device, generating a predictive model based on the plurality of patterns, through deep learning, generating a layout associated with an After Development Inspection (ADI) by correcting the first layout, and predicting an ACI using the layout of ADI, through the predictive model.

公开(公告)号：US20230402097A1

公开(公告)日：2023-12-14

申请号：US18190398

申请日：2023-03-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sooyong LEE ,  Kyung Jae PARK ,  Yongjin CHO

IPC: G11C16/04 ,  H10B43/10 ,  H01L23/528 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

CPC classification number: G11C16/0483 ,  H10B43/10 ,  H01L23/5283 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H01L25/0652

Abstract: Disclosed are a semiconductor device and an electronic system including the same. The semiconductor device may include a stack on a substrate and extending in a first direction, the stack including electrodes vertically stacked on the substrate, string selection lines that are on the stack, extend parallel to the first direction, and are spaced apart from each other in a second direction crossing the first direction, an upper separation pattern that is on the stack, extends in the first direction, and is between the string selection lines, lower vertical structures in the stack, and upper vertical structures in the string selection lines and electrically connected to the lower vertical structures, respectively.

公开(公告)号：US20220382249A1

公开(公告)日：2022-12-01

申请号：US17566151

申请日：2021-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sooyong LEE ,  Mi-Jin KWON ,  Dongho KIM ,  Seunghune YANG

IPC: G05B19/4099

Abstract: A method for manufacturing a semiconductor device, includes receiving a first layout including patterns for the manufacturing of the semiconductor device, generating a second layout by performing machine learning-based process proximity correction (PPC) based on features of the patterns of the first layout, generating a third layout by performing optical proximity correction (OPC) on the second layout, and performing a multiple patterning process based on the third layout. The multiple patterning process includes patterning first-type patterns, and patterning second-type patterns. The machine learning-based process proximity correction is performed based on features of the first-type patterns and features of the second-type patterns.

公开(公告)号：US20210334444A1

公开(公告)日：2021-10-28

申请号：US17112048

申请日：2020-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooyong LEE ,  Jeeyong LEE ,  Jaeho JEONG

IPC: G06F30/392 ,  G06N20/00 ,  G06N5/04 ,  G03F7/20

Abstract: Disclosed is a method for fabricating of a semiconductor device. The method includes receiving a first layout including patterns for the fabrication of the semiconductor device, performing machine learning-based process proximity correction (PPC) based on features of the patterns of the first layout to generate a second layout, and performing optical proximity correction (OPC) on the second layout to generate a third layout.

公开(公告)号：US20250094680A1

公开(公告)日：2025-03-20

申请号：US18617946

申请日：2024-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooyong LEE ,  Jaeyong JEONG

IPC: G06F30/392 ,  G06F30/398 ,  G06F119/18

Abstract: Disclosed is an operating method of an electronic device which includes a processor and supports manufacture of a semiconductor device. The method includes receiving, at the processor, layout data for the manufacture of the semiconductor device, feature data of the layout data, and skew data after the semiconductor device is manufactured; inferring, at the processor, a center and a distribution of a skew of each of patterns and/or edges of the layout data based on the layout data and the feature data, by using a deep learning module; calculating, at the processor, a loss based on the center and the distribution of the skew based on the skew data, and training, at the processor, the deep learning module based on the loss, and the layout data, the feature data, and the skew data are formatted as tabular data.

公开(公告)号：US20230028712A1

公开(公告)日：2023-01-26

申请号：US17701520

申请日：2022-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooyong LEE ,  Dongho KIM ,  Sangwook KIM ,  Jungmin KIM ,  Seunghune YANG ,  Jeeyong LEE ,  Changmook YIM ,  Yangwoo HEO

IPC: G06F30/392 ,  G03F7/20

Abstract: Disclosed is an operating method of an electronic device which includes receiving a design layout for manufacturing the semiconductor device, generating a first layout by performing machine learning-based process proximity correction (PPC), generating a second layout by performing optical proximity correction (OPC), and outputting the second layout for a semiconductor process. The generating of the first layout includes generating a first after cleaning inspection (ACI) layout by executing a machine learning-based process proximity correction module on the design layout, generating a second after cleaning inspection layout by adjusting the design layout based on a difference of the first after cleaning inspection layout and the design layout and executing the process proximity correction module on the adjusted layout, and outputting the adjusted layout as the first layout, when a difference between the second after cleaning inspection layout and the design layout is smaller than or equal to a threshold value.

公开(公告)号：US20170124990A1

公开(公告)日：2017-05-04

申请号：US15342762

申请日：2016-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooyong LEE ,  Jaeseong YOON

IPC: G09G5/397 ,  G09G5/14 ,  G09G5/00 ,  G06F3/147 ,  G06F3/14

CPC classification number: G09G5/397 ,  G06F3/1431 ,  G06F3/1438 ,  G06F3/1446 ,  G06F3/147 ,  G09G5/006 ,  G09G5/14

Abstract: An electronic device is provided which includes a plurality of displays, a processor electrically connected to the plurality of displays, and a memory electrically connected to the processor, in which the memory stores a middleware, which when executed by a processor divides image data to be displayed on the plurality of displays, and transmits the divided image data to display drivers of the plurality of displays.

公开(公告)号：US20240020450A1

公开(公告)日：2024-01-18

申请号：US18360209

申请日：2023-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooyong LEE ,  Jeeyong LEE ,  Jaeho JEONG

IPC: G06F30/392 ,  G06N20/00 ,  G03F7/00 ,  G06N5/04

CPC classification number: G06F30/392 ,  G06N20/00 ,  G03F7/70441 ,  G06N5/04 ,  G06F2119/18

Abstract: Disclosed is a method for fabricating of a semiconductor device. The method includes receiving a first layout including patterns for the fabrication of the semiconductor device, performing machine learning-based process proximity correction (PPC) based on features of the patterns of the first layout to generate a second layout, and performing optical proximity correction (OPC) on the second layout to generate a third layout.

公开(公告)号：US20230395496A1

公开(公告)日：2023-12-07

申请号：US18133314

申请日：2023-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooyong LEE

IPC: H01L23/528 ,  H10B43/10 ,  H01L23/522 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B80/00 ,  H01L25/065

CPC classification number: H01L23/5283 ,  H10B43/10 ,  H01L23/5226 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B80/00 ,  H01L25/0652

Abstract: A semiconductor device is provided. The semiconductor device includes: a first structure including a substrate, circuit elements on the substrate, and lower interconnections on the circuit elements; and a second structure on the first structure, the second structure including: a source structure having a first region and a second region; gate electrodes provided on the source structure and spaced apart from each other, extending in a first direction parallel to an upper surface of the substrate, and including pad regions forming a step structure on the second region; separation patterns passing through the gate electrodes and extending in the first direction; first vertical structures provided between the separation patterns on the first region and extending through the gate electrodes; and second vertical structures provided between the separation patterns, on the second region and extending through the pad regions of the gate electrodes, the second vertical structures and the first vertical structures having a common lattice arrangement

公开(公告)号：US20220179301A1

公开(公告)日：2022-06-09

申请号：US17382773

申请日：2021-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sooyong LEE ,  Bong-Soo KANG

IPC: G03F1/36 ,  H01L21/8234

Abstract: A method of fabricating a semiconductor device includes performing an optical proximity correction (OPC) operation on a design pattern of a layout, and forming a photoresist pattern on a substrate, using a photomask which is manufactured with the layout corrected by the OPC operation. The OPC operation includes generating a target pattern based on the design pattern, performing a first OPC operation, based on the target pattern, to generate a first correction pattern, measuring a target error by comparing a first simulation image of the first correction pattern with the target pattern, generating a retarget pattern from the target pattern, based on the target error, and performing a second OPC operation, based on the retarget pattern, to generate a second correction pattern.