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    SEMICONDUCTOR DEVICES HAVING PARALLEL-TO-SERIAL CONVERTERS THEREIN
    11.
    发明公开
    SEMICONDUCTOR DEVICES HAVING PARALLEL-TO-SERIAL CONVERTERS THEREIN 审中-公开

    公开(公告)号：US20230403010A1

    公开(公告)日：2023-12-14

    申请号：US18175795

    申请日：2023-02-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunyoon Cho ,  Eunseok Shin ,  Youngdon Choi ,  Jaeduk Han ,  Hyuntae Kim ,  Jeonghyu Yang ,  Sanghun Lee

    IPC: H03K19/096 ,  H03K5/15

    CPC classification number: H03K19/096 ,  H03K5/15013

    Abstract: A parallel-to-serial converter includes first to fourth input nodes configured to receive first to fourth data input signals, respectively, and an output node configured to output a data output signal. First to fourth logic circuits are provided, which are configured to electrically couple respective ones of the first to fourth input nodes one-at-a-time to the output node, in synchronization with first to fourth clock signals. The first logic circuit includes a first input circuit, a second input circuit, and an output circuit electrically coupled to the first and second input circuits. The output circuit includes a first pull-up transistor and a first pull-down transistor having drain terminals coupled to the output node, a second pull-up transistor connected between a source terminal of the first pull-up transistor and a first power supply node, and a second pull-down transistor connected between a source terminal of the first pull-down transistor and a second power supply node.

    Output drivers and semiconductor memory devices having the same
    15.
    发明授权
    Output drivers and semiconductor memory devices having the same 有权

    公开(公告)号：US11152045B2

    公开(公告)日：2021-10-19

    申请号：US16884887

    申请日：2020-05-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunyoon Cho

    IPC: G11C8/10 ,  H03K17/687 ,  G11C8/18 ,  H03K19/20 ,  H03K19/0185

    Abstract: An output driver includes a main output driver configured to receive data of an internal supply voltage to generate output data of an output supply voltage, and to receive the data of a ground voltage to generate the output data of the ground voltage, a pre-emphasis controller configured to detect a transition of the data from the ground voltage to the internal supply voltage to generate a first pulse signal, and to receive a pre-emphasis enable signal and the first pulse signal and generate a level-up pre-emphasis enable signal and a first level-up pulse signal of the ground voltage, a pre-emphasis pre-driver configured to generate one or more pre-emphasis pull-up control signals, and a pre-emphasis driver configured to pre-emphasize the output data based on the output data transitioning from the ground voltage to the output supply voltage.

    Receiver for receiving multi-level signal and memory device including the same
    16.
    发明授权
    Receiver for receiving multi-level signal and memory device including the same 有权

    公开(公告)号：US11972831B2

    公开(公告)日：2024-04-30

    申请号：US17827126

    申请日：2022-05-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunsub Rie ,  Eunseok Shin ,  Youngdon Choi ,  Changsoo Yoon ,  Hyunyoon Cho ,  Junghwan Choi

    IPC: G11C7/06 ,  G11C7/10 ,  G11C7/14

    CPC classification number: G11C7/062 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1063 ,  G11C7/109 ,  G11C7/14

    Abstract: A receiver that receives a multi-level signal includes a pre-amplifier circuit, a slicer circuit and a decoder circuit. The pre-amplifier circuit generates a plurality of intermediate data signals based on an input data signal and a plurality of reference voltages. The slicer circuit generates a plurality of decision signals based on the plurality of intermediate data signals and a clock signal. The decoder circuit generates output data based on the plurality of decision signals. The pre-amplifier circuit includes a first circuit and a second circuit. The first circuit generates one of the plurality of intermediate data signals based on the input data signal and one of the plurality of reference voltages, and has a first structure. The second circuit generates another one of the plurality of intermediate data signals based on the input data signal and another one of the plurality of reference voltages, and has a second structure different from the first structure.

    Delay circuit and clock error correction device including the same
    17.
    发明授权
    Delay circuit and clock error correction device including the same 有权

    公开(公告)号：US11791811B2

    公开(公告)日：2023-10-17

    申请号：US17806827

    申请日：2022-06-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunsub Rie ,  Eunseok Shin ,  Youngdon Choi ,  Junyoung Park ,  Hyunyoon Cho ,  Junghwan Choi

    IPC: H03K5/156 ,  G11C7/22 ,  H03K5/135 ,  H03K3/017 ,  H03K5/00

    CPC classification number: H03K5/1565 ,  G11C7/222 ,  H03K3/017 ,  H03K5/135 ,  H03K2005/00241

    Abstract: A delay circuit for a clock signal includes a first signal generator, a first inverting circuit, a second signal generator and a second inverting circuit. The first signal generator is configured to generate a plurality of first switching signals based on a delay code. The first inverting circuit includes a plurality of first inverters that are selectively turned on in response to the plurality of first switching signals, respectively, and is configured to adjust a first delay time for both of a first edge and a second edge of the clock signal. The second signal generator is configured to generate a plurality of second switching signals based on a duty code. The second inverting circuit includes a plurality of second pull-up units and a plurality of second pull-down units, respective ones of the plurality of second pull-up units or respective ones of the plurality of second pull-down units are selectively turned on in response to respective ones of the plurality of second switching signals. The second inverting circuit is configured to adjust a second delay time for the first edge, the second edge, or both of the first edge and the second edge of the clock signal.

    RECEIVER FOR RECEIVING MULTI-LEVEL SIGNAL AND MEMORY DEVICE INCLUDING THE SAME
    18.
    发明申请
    RECEIVER FOR RECEIVING MULTI-LEVEL SIGNAL AND MEMORY DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20230120821A1

    公开(公告)日：2023-04-20

    申请号：US17827126

    申请日：2022-05-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： HYUNSUB RIE ,  Eunseok Shin ,  Youngdon Choi ,  Changsoo Yoon ,  Hyunyoon Cho ,  Junghwan Choi

    IPC: G11C7/06 ,  G11C7/10 ,  G11C7/14

    Abstract: A receiver that receives a multi-level signal includes a pre-amplifier circuit, a slicer circuit and a decoder circuit. The pre-amplifier circuit generates a plurality of intermediate data signals based on an input data signal and a plurality of reference voltages. The slicer circuit generates a plurality of decision signals based on the plurality of intermediate data signals and a clock signal. The decoder circuit generates output data based on the plurality of decision signals. The pre-amplifier circuit includes a first circuit and a second circuit. The first circuit generates one of the plurality of intermediate data signals based on the input data signal and one of the plurality of reference voltages, and has a first structure. The second circuit generates another one of the plurality of intermediate data signals based on the input data signal and another one of the plurality of reference voltages, and has a second structure different from the first structure.

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