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    Method of fabricating a three-dimentional semiconductor memory device
    12.
    发明授权
    Method of fabricating a three-dimentional semiconductor memory device 有权
    制造三维半导体存储器件的方法

    公开(公告)号：US08728893B2

    公开(公告)日：2014-05-20

    申请号：US13775453

    申请日：2013-02-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byoungkeun Son ,  Jinho Kim ,  Hansoo Kim ,  Wonjun Lee ,  Daehyun Jang

    IPC: H01L21/336

    CPC classification number: H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/42336 ,  H01L29/42352 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7889 ,  H01L29/7926

    Abstract: A method of fabricating a semiconductor memory device includes alternately and repeatedly stacking sacrificial layers and insulating layers on a substrate, forming an active pattern penetrating the sacrificial layers and the insulating layers, continuously patterning the insulating layers and the sacrificial layers to form a trench, removing the sacrificial layers exposed in the trench to form recess regions exposing a sidewall of the active pattern, forming an information storage layer on the substrate, forming a gate conductive layer on the information storage layer, such that the gate conductive layer fills the recess regions and defines an empty region in the trench, the empty region being surrounded by the gate conductive layer, and performing an isotropic etch process with respect to the gate conductive layer to form gate electrodes in the recess regions, such that the gate electrodes are separated from each other.

    Abstract translation: 一种制造半导体存储器件的方法包括在衬底上交替地和重复堆叠牺牲层和绝缘层，形成穿透牺牲层和绝缘层的有源图案，连续地图案化绝缘层和牺牲层以形成沟槽，去除 所述牺牲层暴露在所述沟槽中以形成暴露所述有源图案的侧壁的凹陷区域，在所述衬底上形成信息存储层，在所述信息存储层上形成栅极导电层，使得所述栅极导电层填充所述凹部区域， 在沟槽中限定空区域，空区域被栅极导电层包围，并且相对于栅极导电层执行各向同性蚀刻处理，以在凹陷区域中形成栅电极，使得栅电极与每个栅电极分离 其他。

    Method of fabricating three-dimensional semiconductor memory device
    13.
    发明授权
    Method of fabricating three-dimensional semiconductor memory device 审中-公开

    公开(公告)号：US10672790B2

    公开(公告)日：2020-06-02

    申请号：US16180609

    申请日：2018-11-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Han Geun Yu ,  Daehyun Jang

    IPC: H01L21/311 ,  H01L21/033 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/10 ,  H01L21/02

    Abstract: Methods of fabricating a three-dimensional semiconductor memory device are provided. A method may include forming a mold structure on a substrate including channel regions and a non-channel region between the channel regions, and forming, on the mold structure, a multilayered mask layer including a first mask layer, an etch stop layer, and a second mask layer that are sequentially stacked. The multilayered mask layer may include mask holes exposing the mold structure in the channel regions, dummy mask holes exposing the first mask layer in the non-channel region, and buffer spacers covering sidewalls of the second mask layer exposed by the mask holes and the dummy mask holes. The method may include etching the mold structure using the multilayered mask layer as an etch mask to form channel holes in the channel regions.

    Semiconductor memory devices and methods of forming the same
    14.
    发明授权
    Semiconductor memory devices and methods of forming the same 有权
    半导体存储器件及其形成方法

    公开(公告)号：US09466612B2

    公开(公告)日：2016-10-11

    申请号：US14985730

    申请日：2015-12-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung Ho Kim ,  Daehyun Jang ,  Myoungbum Lee ,  Kihyun Hwang ,  Sangryol Yang ,  Yong-Hoon Son ,  Ju-Eun Kim ,  Sunghae Lee ,  Dongwoo Kim ,  JinGyun Kim

    IPC: H01L29/76 ,  H01L27/115 ,  H01L29/792 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324

    CPC classification number: H01L27/11582 ,  H01L21/02675 ,  H01L21/30604 ,  H01L21/324 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/7926

    Abstract: Methods of forming semiconductor devices may be provided. A method of forming a semiconductor device may include patterning first and second material layers to form a first through region exposing a substrate. The method may include forming a first semiconductor layer in the first through region on the substrate and on sidewalls of the first and second material layers. In some embodiments, the method may include forming a buried layer filling the first through region on the first semiconductor layer. In some embodiments, the method may include removing a portion of the buried layer to form a second through region between the sidewalls of the first and second material layers. Moreover, the method may include forming a second semiconductor layer in the second through region.

    Abstract translation: 可以提供形成半导体器件的方法。 形成半导体器件的方法可以包括图案化第一和第二材料层以形成暴露衬底的第一穿透区域。 该方法可以包括在衬底上的第一至区域中以及在第一和第二材料层的侧壁上形成第一半导体层。 在一些实施例中，该方法可以包括形成填充第一半导体层上的第一通过区域的掩埋层。 在一些实施例中，该方法可以包括移除掩埋层的一部分以在第一和第二材料层的侧壁之间形成第二穿透区域。 此外，该方法可以包括在第二通过区域中形成第二半导体层。

    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FORMING THE SAME
    15.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FORMING THE SAME 审中-公开
    半导体存储器件及其形成方法

    公开(公告)号：US20160118400A1

    公开(公告)日：2016-04-28

    申请号：US14985730

    申请日：2015-12-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung Ho Kim ,  Daehyun Jang ,  Myoungbum Lee ,  Kihyun Hwang ,  Sangryol Yang ,  Yong-Hoon Son ,  Ju-Eun Kim ,  Sunghae Lee ,  Dongwoo Kim ,  JinGyun Kim

    IPC: H01L27/115 ,  H01L21/306 ,  H01L21/324

    CPC classification number: H01L27/11582 ,  H01L21/02675 ,  H01L21/30604 ,  H01L21/324 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/7926

    Abstract: Methods of forming semiconductor devices may be provided. A method of forming a semiconductor device may include patterning first and second material layers to form a first through region exposing a substrate. The method may include forming a first semiconductor layer in the first through region on the substrate and on sidewalls of the first and second material layers. In some embodiments, the method may include forming a buried layer filling the first through region on the first semiconductor layer. In some embodiments, the method may include removing a portion of the buried layer to form a second through region between the sidewalls of the first and second material layers. Moreover, the method may include forming a second semiconductor layer in the second through region.

    Abstract translation: 可以提供形成半导体器件的方法。 形成半导体器件的方法可以包括图案化第一和第二材料层以形成暴露衬底的第一穿透区域。 该方法可以包括在衬底上的第一至区域中以及在第一和第二材料层的侧壁上形成第一半导体层。 在一些实施例中，该方法可以包括形成填充第一半导体层上的第一通过区域的掩埋层。 在一些实施例中，该方法可以包括移除掩埋层的一部分以在第一和第二材料层的侧壁之间形成第二穿透区域。 此外，该方法可以包括在第二通过区域中形成第二半导体层。

    SEMICONDUCTOR DEVICE HAVING WORD LINE SEPARATION LAYER
    18.
    发明申请
    SEMICONDUCTOR DEVICE HAVING WORD LINE SEPARATION LAYER 有权

    公开(公告)号：US20230032392A1

    公开(公告)日：2023-02-02

    申请号：US17934959

    申请日：2022-09-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jiye Noh ,  Jinsoo Lim ,  Daehyun Jang ,  Jisung Cheon ,  Sangjun Hong

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/528 ,  H01L23/48

    Abstract: A semiconductor device includes a peripheral circuit structure; a lower stack disposed on the peripheral circuit structure and an upper stack disposed in the lower stack including a plurality of lower insulating layers and a plurality of lower word lines alternately stacked with the lower insulating layers; a plurality of channel structures extending through the lower stack and the upper stack in the cell array area; a pair of separation insulating layers extending vertically through the lower stack and the upper stack and extending in a horizontal direction, the pair of separation insulating layers being spaced apart from each other in a vertical direction; and a word line separation layer disposed at an upper portion of the lower stack and crossing the pair of separation insulating layers when viewed in a plan view, the word line separation layer extending vertically through at least one of the lower word lines.

    Semiconductor device having word line separation layer
    20.
    发明授权
    Semiconductor device having word line separation layer 有权

    公开(公告)号：US11456316B2

    公开(公告)日：2022-09-27

    申请号：US16926045

    申请日：2020-07-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jiye Noh ,  Jinsoo Lim ,  Daehyun Jang ,  Jisung Cheon ,  Sangjun Hong

    IPC: H01L27/11582 ,  H01L23/48 ,  H01L23/528 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11565

    Abstract: A semiconductor device includes a peripheral circuit structure disposed on a substrate; a lower stack disposed on the peripheral circuit structure and an upper stack disposed in the lower stack, the lower stack including a plurality of lower insulating layers and a plurality of lower word lines alternately stacked with the lower insulating layers; a plurality of channel structures extending through the lower stack and the upper stack in the cell array area; a pair of separation insulating layers extending vertically through the lower stack and the upper stack and extending in a horizontal direction, the pair of separation insulating layers being spaced apart from each other in a vertical direction; and a word line separation layer disposed at an upper portion of the lower stack and crossing the pair of separation insulating layers when viewed in a plan view, the word line separation layer extending vertically through at least one of the lower word lines.

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