公开(公告)号：US20240065001A1

公开(公告)日：2024-02-22

申请号：US18299403

申请日：2023-04-12

Applicant: SAMSUNG ELECTRONICS CO,LTD.

Inventor： Seyun KIM ,  Jooheon KANG ,  Sunho KIM ,  Yumin KIM ,  Garam PARK ,  Hyunjae SONG ,  Dongho AHN ,  Seungyeul YANG ,  Myunghun WOO ,  Jinwoo LEE

IPC: H10B63/00

CPC classification number: H10B63/845 ,  H10B63/34

Abstract: Provided area a variable resistance memory device and/or an electronic device including the same. The variable resistance memory device includes: a resistance change layer including a metal oxide having an oxygen deficient ratio greater than or equal to about 9%; a semiconductor layer on the resistance change layer; a gate insulating layer on the semiconductor layer; and a plurality of electrodes on the gate insulating layer to be apart from each other.

公开(公告)号：US20230225138A1

公开(公告)日：2023-07-13

申请号：US18185817

申请日：2023-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yumin KIM ,  Seyun KIM ,  Jinhong KIM ,  Soichiro MIZUSAKI ,  Youngjin CHO

IPC: H01L47/00

CPC classification number: H10B63/84 ,  H10B63/34 ,  H10N70/011 ,  H10N70/8833 ,  H10N70/231 ,  H10N70/8828 ,  H10N70/841

Abstract: A memory device may include an insulating structure including a first surface and a protrusion portion protruding from the first surface in a first direction, a recording material layer on the insulating structure and extending along a protruding surface of the protrusion portion to cover the protrusion portion and extending onto the first surface of the insulating structure, a channel layer on the recording material layer and extending along a surface of the recording material layer, a gate insulating layer on the channel layer; and a gate electrode formed on the gate insulating layer at a location facing a second surface of the insulating structure. The second surface of the insulating structure may be a protruding upper surface of the protrusion portion.

公开(公告)号：US20230121581A1

公开(公告)日：2023-04-20

申请号：US17741847

申请日：2022-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seyun KIM ,  Doyoon KIM ,  Yumin KIM ,  Hyunjae SONG ,  Seungyeul YANG

IPC: H01L27/24

Abstract: A variable resistance memory device includes: a supporting layer including an insulating material; a variable resistance layer on the supporting layer and including a first layer including a metal oxide and metal nanoparticles, the variable resistance layer including a second layer on the first layer and including an oxide; a channel layer on the variable resistance layer; a gate insulating layer on the channel layer; and a gate electrode on the gate insulating layer. The metal nanoparticles in the variable resistance layer include a first metal capable of combining with oxygen ions of the metal oxide, thereby increasing oxygen vacancies.

公开(公告)号：US20220302380A1

公开(公告)日：2022-09-22

申请号：US17395040

申请日：2021-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soichiro MIZUSAKI ,  Doyoon KIM ,  Seyun KIM ,  Yumin KIM ,  Jinhong KIM ,  Youngjin CHO

IPC: H01L45/00 ,  H01L27/24

Abstract: A variable resistance memory may include first and second conductive elements spaced apart from each other on a variable resistance layer. The variable resistance layer may include first to third oxide layers sequentially arranged in a direction perpendicular to a direction in which the first and second conductive elements are arranged. A dielectric constant of the second oxide layer may be greater than dielectric constants of the first and third oxide layers.

公开(公告)号：US20220246679A1

公开(公告)日：2022-08-04

申请号：US17523381

申请日：2021-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjin CHO ,  Seyun KIM ,  Yumin KIM ,  Doyoon KIM ,  Jinhong KIM ,  Soichiro MIZUSAKI

IPC: H01L27/24 ,  H01L45/00

Abstract: A variable resistance memory device includes a support layer including an insulating material; a variable resistance layer on the support layer and including a variable resistance material; a capping layer between the support layer and the variable resistance layer and protecting the variable resistance layer; a channel layer on the variable resistance layer; a gate insulating layer on the channel layer; and a plurality of gate electrodes and a plurality of insulators alternately and repeatedly arranged on the gate insulating layer in a first direction parallel with the channel layer. The capping layer may maintain oxygen vacancies formed in the variable resistance layer.

公开(公告)号：US20220020437A1

公开(公告)日：2022-01-20

申请号：US17306302

申请日：2021-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yumin KIM ,  Seyun KIM ,  Jinhong KIM ,  Soichiro MIZUSAKI ,  Youngjin CHO

IPC: G11C16/26 ,  G11C16/30 ,  G11C16/24 ,  G11C16/14 ,  G11C16/04 ,  G11C5/06

Abstract: A nonvolatile memory device and an operating method thereof are provided. The nonvolatile memory device includes a memory cell array including first to third memory cells sequentially arranged in a vertical stack structure and a control logic configured to apply a first non-selection voltage to the first memory cell, apply a second non-selection voltage different from the first non-selection voltage to the third memory cell, apply a selection voltage to the second memory cell, and select the second memory cell as a selection memory cell.