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    SEMICONDUCTOR INTEGRATED CIRCUIT
    11.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 有权

    公开(公告)号：US20130169247A1

    公开(公告)日：2013-07-04

    申请号：US13674766

    申请日：2012-11-12

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Masafumi Onouchi ,  Kazuo Otsuga ,  Yasuto Igarashi ,  Sadayuki Morita ,  Koichiro Ishibashi ,  Kazumasa Yanagisawa

    IPC: G05F1/59

    CPC classification number: G05F1/59 ,  G06F1/26 ,  H01L23/5286 ,  H01L2924/0002 ,  H02M2001/0045 ,  H03K17/102 ,  H01L2924/00

    Abstract: A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance.

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    15.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20170179136A1

    公开(公告)日：2017-06-22

    申请号：US15448585

    申请日：2017-03-02

    Applicant: Renesas Electronics Corporation

    Inventor： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    IPC: H01L27/11 ,  H01L29/49 ,  H01L29/78 ,  G11C11/412

    CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

    Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    16.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权

    公开(公告)号：US20160329091A1

    公开(公告)日：2016-11-10

    申请号：US15216327

    申请日：2016-07-21

    Applicant: Renesas Electronics Corporation

    Inventor： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    IPC: G11C11/412 ,  H01L27/11

    CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

    Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

    Semiconductor memory device that can stably perform writing and reading without increasing current consumption even with a low power supply voltage
    17.
    发明授权
    Semiconductor memory device that can stably perform writing and reading without increasing current consumption even with a low power supply voltage 有权
    半导体存储器件即使在低电源电压下也能够稳定地执行写入和读取而不增加电流消耗

    公开(公告)号：US09218873B2

    公开(公告)日：2015-12-22

    申请号：US14151581

    申请日：2014-01-09

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Koji Nii ,  Shigeki Obayashi ,  Hiroshi Makino ,  Koichiro Ishibashi ,  Hirofumi Shinohara

    IPC: G11C5/14 ,  G11C11/412 ,  G11C5/06 ,  G11C11/419

    CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C11/412

    Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

    Abstract translation: 单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。 在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。 即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。

    Semiconductor integrated circuit
    19.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US09030176B2

    公开(公告)日：2015-05-12

    申请号：US13674766

    申请日：2012-11-12

    Applicant: Renesas Electronics Corporation

    Inventor： Masafumi Onouchi ,  Kazuo Otsuga ,  Yasuto Igarashi ,  Sadayuki Morita ,  Koichiro Ishibashi ,  Kazumasa Yanagisawa

    IPC: G05F1/00 ,  G05F1/59

    CPC classification number: G05F1/59 ,  G06F1/26 ,  H01L23/5286 ,  H01L2924/0002 ,  H02M2001/0045 ,  H03K17/102 ,  H01L2924/00

    Abstract: A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance.

    Abstract translation: 半导体集成电路包括多个输出晶体管，每个输出晶体管根据施加到控制端子的阻抗控制信号所指示的控制值来控制输出电压的大小相对于负载电流的大小;电压监视电路，输出输出 表示输出电压的电压值的电压监视值，以及根据表示输出电压的目标值的基准电压与输出电压监视值之间的误差值的大小来控制控制值的大小的控制电路， 并且基于控制值来控制是否任何这种晶体管进入导通状态。 控制电路根据预先通知负载电流变化的预通知信号，在预定期间内增加控制值相对于误差值的变化步长。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    20.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20180261607A1

    公开(公告)日：2018-09-13

    申请号：US15975761

    申请日：2018-05-09

    Applicant: Renesas Electronics Corporation

    Inventor： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    IPC: H01L27/11 ,  H01L29/49 ,  H01L29/78 ,  G11C11/412 ,  G11C11/417

    CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

    Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

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