公开(公告)号：US10686031B2

公开(公告)日：2020-06-16

申请号：US15937097

申请日：2018-03-27

Applicant: QUALCOMM Incorporated

Inventor： Peijie Feng ,  Junjing Bao ,  Ye Lu ,  Giridhar Nallapati

IPC: H01L49/02 ,  H01L23/522

Abstract: A capacitor includes first conductive fingers interdigitated with second conductive fingers at an Mx interconnect level, and third conductive fingers interdigitated with fourth conductive fingers at an Mx-1 interconnect level. The third conductive fingers are offset from the first conductive fingers. The second conductive fingers are offset from the fourth conductive fingers. The capacitor further includes fifth conductive fingers interdigitated with sixth conductive fingers at an Mx-2 interconnect level. The fifth conductive fingers are offset from the third conductive fingers. The sixth conductive fingers are offset from the fourth conductive fingers. The capacitor further includes seventh conductive fingers interdigitated with eighth conductive fingers at an Mx-3 interconnect level. The seventh conductive fingers are offset from the fifth conductive fingers. The eighth conductive fingers are offset from the sixth conductive fingers. A first set of vias electrically couples the first conductive fingers to the fifth conductive fingers.

公开(公告)号：US10600569B2

公开(公告)日：2020-03-24

申请号：US15961594

申请日：2018-04-24

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Haitao Cheng ,  Chao Song

IPC: H01L23/52 ,  H01G4/10 ,  H01L23/522 ,  H01G4/01

Abstract: Methods, systems, and devices for a finger metal-on-metal (FMOM) capacitor including a negative capacitance material are described. In one examples, a FMOM capacitor may include a first electrode and a second electrode. The FMOM capacitor may include a dielectric layer coating a first sidewall of the first electrode and a second sidewall of a second electrode. A portion of the first sidewall may be substantially parallel to a portion of the second sidewall. The FMOM capacitor may also include a negative capacitance material disposed in a channel between the first sidewall of the first electrode and the second sidewall of the second electrode. The negative capacitance material may extend in a direction that is substantially parallel to the portion of the first sidewall and the portion of the second sidewall.

公开(公告)号：US10566413B2

公开(公告)日：2020-02-18

申请号：US15724147

申请日：2017-10-03

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Junjing Bao ,  Bin Yang

IPC: H01L49/02 ,  H01L21/321 ,  H01L21/768 ,  H01L27/11502 ,  H01L27/108 ,  H01L29/66 ,  H01L23/522 ,  H01L29/94 ,  H01L27/08

Abstract: A capacitor may include a first conductive layer forming a first capacitor plate, a second conductive layer forming a second capacitor plate, and a first insulating material on the first conductive layer. The first insulating material may include a positive capacitance material. The capacitor may further include a second insulating material disposed over the first insulating material and between the first insulating material and the second conductive layer. The second insulating material may include a negative capacitance ferroelectric material.

公开(公告)号：US11562205B2

公开(公告)日：2023-01-24

申请号：US16576597

申请日：2019-09-19

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  Ye Lu

IPC: G06N3/04 ,  G06F7/544 ,  G06F17/15

Abstract: An apparatus includes first and second compute-in-memory (CIM) arrays. The first CIM array is configured to store weights corresponding to a filter tensor, to receive a first set of activations corresponding to a first receptive field of an input, and to process the first set of activations with the weights to generate a corresponding first tensor of output values. The second CIM array is configured to store a first copy of the weights corresponding to the filter tensor and to receive a second set of activations corresponding to a second receptive field of the input. The second CIM array is also configured to process the second set of activations with the first copy of the weights to generate a corresponding second tensor of output values. The first and second compute-in-memory arrays are configured to process the first and second receptive fields in parallel.

公开(公告)号：US11500960B2

公开(公告)日：2022-11-15

申请号：US16666699

申请日：2019-10-29

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  Ye Lu ,  Yandong Gao ,  Xiaochun Zhu ,  Xia Li

IPC: G11C11/419 ,  G06F17/16 ,  G11C11/412 ,  G06N3/063

Abstract: Certain aspects provide a circuit for in-memory computation. The circuit generally includes an in-memory computation array having a plurality of computation circuits, each of the computation circuits being configured to perform a dot product computation. In certain aspects, each of the computation circuits includes a memory cell, a capacitive element, a precharge transistor coupled between an output of the memory cell and the capacitive element, and a read transistor coupled between a read bit line (RBL) and the capacitive element.

公开(公告)号：US11296083B2

公开(公告)日：2022-04-05

申请号：US16811762

申请日：2020-03-06

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Lixin Ge ,  Kwanyong Lim ,  Jun Chen

IPC: H01L27/092 ,  H01L23/522 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06

Abstract: 3D vertically-integrated FETs electrically coupled by integrated vertical FET-to-FET interconnects for reducing an area of CMOS cell circuits are disclosed. Vertically integrated FETs reduce a footprint area of an integrated circuit chip. The FETs include horizontal channel structures that are vertically integrated by stacking a second channel structure of a second FET above a first channel structure of a first FET. The first and second FETs can include a combination of a PFET and NFET that can be used to form a 3D CMOS cell circuit as an example. The area occupied by the 3D CMOS cell circuit includes interconnects for electrically coupling terminal regions of the FETs internally and externally. Vertical FET-to-FET interconnects extend between the FETs to electrically couple terminal regions of the FETs to reduce a number of vias from a semiconductor layer of the 3D CMOS cell circuit to metal interconnect layers above the vertically-integrated FETs.

公开(公告)号：US11239307B2

公开(公告)日：2022-02-01

申请号：US16866316

申请日：2020-05-04

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Ye Lu ,  Junjing Bao

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

Abstract: Certain aspects of the present disclosure generally relate to a metal-oxide-metal (MOM) capacitor formed from a subtractive back-end-of-line (BEOL) scheme. One example method of fabricating a semiconductor device generally includes forming an active layer and forming a capacitive element above the active layer with a back-end-of-line subtractive process for conductive materials.

公开(公告)号：US11164952B2

公开(公告)日：2021-11-02

申请号：US16812292

申请日：2020-03-07

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Haining Yang ,  Junjing Bao

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

Abstract: A gate all around transistor may be improved to provide better transistor circuits performance. In one example, a transistor circuit may include a dielectric or air gap as an insulator between the channels of the transistors in the circuit. In another example, a transistor may include a first channel surrounded by a first metal, a second channel surrounded by a second metal proximate to the first channel, and an insulator, such as a dielectric or air gap, between the first metal and the second metal. The insulator helps reduce the parasitic capacitance between the source/drain regions and the metal fill regions of the transistor.

公开(公告)号：US10896949B2

公开(公告)日：2021-01-19

申请号：US16106160

申请日：2018-08-21

Applicant: QUALCOMM Incorporated

Inventor： Haitao Cheng ,  Chao Song ,  Ye Lu

IPC: H01L49/02 ,  H01F17/00 ,  H01L23/522 ,  H01L27/08

Abstract: Aspects generally relate to adjusting, or lowering, the Q of an inductor. In one embodiment, an integrated circuit includes an inductor and a conductive closed ring inside a periphery of the inductor. In another embodiment, there can be a plurality of closed rings inside the periphery of the inductor. The conductive closed rings are magnetically coupled to the inductor to adjust the Q.

公开(公告)号：US20190378904A1

公开(公告)日：2019-12-12

申请号：US16002459

申请日：2018-06-07

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Ye Lu ,  Lixin Ge

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49

Abstract: A Field-Effect Transistor (FET) with a negative capacitance layer to increase power density provides a negative capacitor connected in series with a conventional positive capacitor. The dimensions of the negative capacitor are controlled to allow the difference in capacitances between the negative capacitor and the positive capacitor to approach zero, which in turn provides a large total capacitance. The large total capacitance provides for increased power density.