公开(公告)号：US20210210449A1

公开(公告)日：2021-07-08

申请号：US17027316

申请日：2020-09-21

Applicant: QUALCOMM Incorporated

Inventor： Dongming HE ,  Hung-Yuan HSU ,  Yangyang SUN ,  Wei HU ,  Wei WANG ,  Lily ZHAO

IPC: H01L23/00

Abstract: A thermal compression flip chip (TCFC) bump may be used for high performance products that benefit from a fine pitch. In one example, a new TCFC bump structure adds a metal pad underneath the TCFC copper pillar bump to cover the exposed aluminum bump pad. This new structure prevents the pad from corroding and reduces mechanical stress to the pad and underlying silicon dielectric layers enabling better quality and reliability and further bump size reduction. For example, a flip chip connection may include a substrate; a metal pad on a contact side of the substrate and a first passivation layer on the contact side of the substrate to protect the metal pad from corrosion.

公开(公告)号：US20240355781A1

公开(公告)日：2024-10-24

申请号：US18628469

申请日：2024-04-05

Applicant: QUALCOMM Incorporated

Inventor： Yangyang SUN ,  Xuefeng ZHANG ,  Jun CHEN ,  Lily ZHAO

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2225/06513 ,  H01L2225/06562 ,  H01L2924/1306 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/182

Abstract: A device includes an integrated device. The integrated device includes a die that is at least partially encapsulated. The die includes a conductive pad. The device also includes a first passivation layer coupled to a first surface of the die. The device includes an offset interconnect extending along a surface of the first passivation layer and including a portion that extends through an opening in the first passivation layer to contact the conductive pad. The device includes a bump including a portion that extends through an opening in a second passivation layer to contact the offset interconnect. The bump is offset, in a direction along a surface of the second passive layer, from the conductive pad.

公开(公告)号：US20240006361A1

公开(公告)日：2024-01-04

申请号：US17855189

申请日：2022-06-30

Applicant: QUALCOMM Incorporated

Inventor： Wei WANG ,  Dongming HE ,  Yangyang SUN ,  Wei HU

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/05 ,  H01L24/04 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05022 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13082 ,  H01L2224/1146 ,  H01L2224/11903 ,  H01L24/81 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/81815

Abstract: An integrated device comprising a die portion that includes a plurality of pads and a plurality of under bump metallization interconnects coupled to the plurality of pads, where the plurality of under bump metallization interconnects comprises a first under bump metallization interconnect. The integrated device includes a plurality of pillar interconnects coupled to the plurality of under bump metallization interconnects, where the plurality of pillar interconnects includes a first pillar interconnect. The first pillar interconnect includes a first width that corresponds to a widest part of the first pillar interconnect, and a second width that corresponds to a part of the first pillar interconnect that is vertically farthest away from the first under bump metallization interconnect, wherein the second width is less than the first width.

公开(公告)号：US20230384367A1

公开(公告)日：2023-11-30

申请号：US17804658

申请日：2022-05-31

Applicant: QUALCOMM Incorporated

Inventor： Yangyang SUN ,  Amer Christophe Gaetan CASSIER ,  Stanley Seungchul SONG ,  Lily ZHAO ,  Dongming HE

IPC: G01R31/28 ,  H01L23/00

CPC classification number: G01R31/2884 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2924/1431 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14515 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06515 ,  H01L2224/14131 ,  H01L2224/14132 ,  H01L2224/06131 ,  H01L2224/06132 ,  H01L2224/11916 ,  H01L2224/11903 ,  H01L2224/0401 ,  H01L2224/05573 ,  H01L2224/05005 ,  H01L2224/05017 ,  H01L2224/05073 ,  H01L2224/05541 ,  H01L2224/05557 ,  H01L2224/05147 ,  H01L2224/05124 ,  H01L2224/05647 ,  H01L2224/05624 ,  H01L2224/13147 ,  H01L2224/13005 ,  H01L2224/13016

Abstract: Disclosed are integrated circuit structures with interconnects of small size, also referred to micro-bumps. As pitches of micro-bumps become smaller, their sizes also become small. This makes it difficult to probe the integrated circuit structure to verify their operations. To enable probing, test pads of larger pitches are provided. The test pads, usually formed of metal, may be protected with solder caps.

公开(公告)号：US20230223375A1

公开(公告)日：2023-07-13

申请号：US17574360

申请日：2022-01-12

Applicant: QUALCOMM Incorporated

Inventor： Yangyang SUN ,  Dongming HE ,  Lily ZHAO

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L24/73 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/0657 ,  H01L24/32 ,  H01L24/26 ,  H01L25/50 ,  H01L24/92 ,  H01L2225/06541 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06565 ,  H01L24/30 ,  H01L2224/301 ,  H01L24/33 ,  H01L2224/33181 ,  H01L24/29 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L24/16 ,  H01L2224/16148 ,  H01L24/13 ,  H01L2224/13082 ,  H01L2224/73104 ,  H01L2224/73253 ,  H01L24/06 ,  H01L2224/06181 ,  H01L24/05 ,  H01L2224/0557 ,  H01L2224/26125 ,  H01L2224/9211

Abstract: A package that includes a first integrated device comprising a first plurality of interconnects; a plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device comprising a second plurality of interconnects, wherein the second integrated device is coupled to the first integrated device through the second plurality of interconnects, the plurality of solder interconnects and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; and a plurality of spacer balls located between the first integrated device and the second integrated device.

公开(公告)号：US20210407939A1

公开(公告)日：2021-12-30

申请号：US16917295

申请日：2020-06-30

Applicant: QUALCOMM Incorporated

Inventor： Yangyang SUN ,  Dongming HE ,  Lily ZHAO

IPC: H01L23/00

Abstract: Disclosed is a flip-chip device. The flip-chip device includes a die having a plurality of under bump metallizations (UBMs); and a package substrate having a plurality of bond pads. The plurality of UBMs include a first set of UBMs having a first size and a first minimum pitch and a second set of UBMs having a second size and a second minimum pitch. The first set of UBMs and the second set of UBMs are each electrically coupled to the package substrate by a bond-on-pad connection.

公开(公告)号：US20210125951A1

公开(公告)日：2021-04-29

申请号：US16665883

申请日：2019-10-28

Applicant: QUALCOMM Incorporated

Inventor： Li-Sheng WENG ,  Yue LI ,  Yangyang SUN

IPC: H01L23/00

Abstract: An integrated device that includes a substrate, an interconnect portion and an interconnect structure. The interconnect portion is located over the substrate. The interconnect portion includes a plurality of interconnects and at least one dielectric layer. The interconnect structure is located over the interconnect portion. The interconnect structure includes an inner interconnect, a dielectric layer coupled to the inner interconnect, and an outer conductive layer coupled to the dielectric layer. The outer conductive layer is configured to operate as a shield for the inner interconnect.

公开(公告)号：US20250062285A1

公开(公告)日：2025-02-20

申请号：US18451971

申请日：2023-08-18

Applicant: QUALCOMM Incorporated

Inventor： Yue LI ,  Ryan LANE ,  Yangyang SUN ,  Charles David PAYNTER ,  Durodami LISK

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/16

Abstract: A stacked integrated circuit (IC) device includes a first die having a first face, a first active region adjacent to the first face, and first die-interconnect contacts disposed on the first face and connected to first circuitry. The stacked IC device includes a second die having a second face, a second active region adjacent to the second face, and second die-interconnect contacts disposed on the second face and connected to second circuitry. The first face is oriented toward the second face, and the first die-interconnect contacts are connected to the second die-interconnect contacts. The stacked IC device includes a set of redistribution layers electrically connected to redistribution contacts on the first face, the second face, or both. The stacked IC device also includes interconnect conductors connected to the redistribution layers to provide signal paths from the first die, the second die, or both, to a set of external contacts.

公开(公告)号：US20240297129A1

公开(公告)日：2024-09-05

申请号：US18177005

申请日：2023-03-01

Applicant: QUALCOMM Incorporated

Inventor： Yangyang SUN ,  Amer Christophe Gaetan CASSIER

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L24/30 ,  H01L2224/0348 ,  H01L2224/13028 ,  H01L2224/16054 ,  H01L2224/16055

Abstract: A device comprising an integrated device. The integrated device comprising a die substrate; an interconnect portion coupled to the die substrate, a plurality of pillar interconnects and a passivation layer coupled to the interconnect portion. The interconnect portion includes a first plurality of pads and a second plurality of pads. The first plurality of pads are configured to provide a first plurality of electrical paths for input/output signals. The second plurality of pads are configured to provide a second plurality of electrical paths for power. The plurality of pillar interconnects are coupled to the first plurality of pads and the second plurality of pads. The passivation layer comprises a plurality of openings. The plurality of openings include at least one opening located over a pad from the first plurality of pads.

公开(公告)号：US20230369234A1

公开(公告)日：2023-11-16

申请号：US17741986

申请日：2022-05-11

Applicant: QUALCOMM Incorporated

Inventor： Yangyang SUN ,  Srikanth KULKARNI ,  Lily ZHAO ,  Milind SHAH

IPC: H01L23/538 ,  H01L25/16 ,  H01L21/48 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/5386 ,  H01L25/165 ,  H01L21/486 ,  H01L23/49894 ,  H01L23/3121 ,  H01L23/3135 ,  H01L24/32

Abstract: A package comprising a substrate comprising a first surface and a second surface; a first integrated device coupled to the first surface of the substrate; an interconnection die coupled to the first surface of the substrate; a first encapsulation layer coupled to the first surface of the substrate, wherein the first encapsulation layer encapsulates the first integrated device and the interconnection die; and a second integrated device coupled to the second surface of the substrate.