公开(公告)号：US10050448B2

公开(公告)日：2018-08-14

申请号：US15130549

申请日：2016-04-15

Applicant: QUALCOMM Incorporated

Inventor： Yeshwant Nagaraj Kolla ,  Neel Shashank Natekar ,  Manish Garg

IPC: H02J4/00 ,  G06F1/26 ,  G11C5/14 ,  G06F1/32

Abstract: Power rail control systems that include power multiplexing circuits that include cross-current conduction protection are disclosed. Power multiplexing circuit includes supply selection circuits each coupled between a respective supply power rail and an output power rail coupled to a powered circuit. To maintain power to the powered circuit during switching coupling of the output power rail, but while also avoiding current cross-conduction path between supply power rails, diode drop control circuits are provided in supply selection circuits. In diode drop operation mode, the diode drop control circuit associated with a higher voltage supply power rail is configured to regulate voltage supplied by such supply power rail to the output power rail to power the powered circuit. A current cross-conduction path is not created, because diode drop control circuits associated with lower voltage supply power rails are reverse biased to prevent current from flowing through their associated supply selection circuits.

公开(公告)号：US09911472B1

公开(公告)日：2018-03-06

申请号：US15362795

申请日：2016-11-28

Applicant: QUALCOMM Incorporated

Inventor： Shaoping Ge ,  Chiaming Chai ,  Stephen Edward Liles ,  Manish Garg

IPC: G11C7/12 ,  G11C7/22 ,  G11C7/10

CPC classification number: G11C7/12 ,  G11C5/14 ,  G11C7/1006 ,  G11C7/1096 ,  G11C7/18 ,  G11C7/22

Abstract: Systems and methods are directed to managing signals in a dual voltage domain comprising a high voltage domain and a low voltage domain. A write bitline driver circuit receives complementary global write bitline signals as input signals from a global write bitline driver in the low voltage domain, and a write enable signal as an input signal in the high voltage domain. The write bitline driver circuit generates complementary local write bitline signals as output signals in the high voltage domain for activating bitlines of a memory bank in the high voltage domain. The complementary local write bitline signals are based on the complementary global write bitline signals, voltage level shifted from the low voltage domain to the high voltage domain and gated by the write enable signal.

公开(公告)号：US09129706B2

公开(公告)日：2015-09-08

申请号：US13787875

申请日：2013-03-07

Applicant: QUALCOMM Incorporated

Inventor： Harish Shankar ,  David Paul Hoff ,  Manish Garg

IPC: G11C11/412 ,  G11C5/06 ,  G11C8/16 ,  G11C8/00 ,  G11C8/08 ,  G11C11/413 ,  G11C11/418

CPC classification number: G11C11/412 ,  G11C5/063 ,  G11C8/08 ,  G11C8/16 ,  G11C11/413 ,  G11C11/418

Abstract: Systems and methods for detecting and suppressing crowbar currents in memory arrays. A dummy read is implemented to prevent crowbar currents in the case of simultaneous read-write collisions in a static random access memory (SRAM) array having cross-coupled bitline keepers. When a simultaneous read and write operation to a first entry of the memory array is detected, the read operation to the first entry is suppressed and a dummy read operation to a second entry of the memory array is performed. The write operation to the first entry is allowed to proceed undisturbed.

Abstract translation: 用于检测和抑制存储器阵列中的电涌电流的系统和方法。 在具有交叉耦合的位线保持器的静态随机存取存储器（SRAM）阵列中，实现了虚拟读取以防止在同时读写冲突的情况下的撬棒电流。 当检测到对存储器阵列的第一条目的同时读取和写入操作时，对第一条目的读取操作被抑制，并且执行对存储器阵列的第二条目的伪读取操作。 允许对第一个条目的写入操作不受干扰。

公开(公告)号：US09093125B2

公开(公告)日：2015-07-28

申请号：US13746528

申请日：2013-01-22

Applicant: QUALCOMM Incorporated

Inventor： Joshua L. Puckett ,  Manish Garg ,  Harish Shankar

IPC: G11C7/00 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C7/00 ,  G11C11/412 ,  G11C11/419

Abstract: In low power CPUs, the best way to reduce power is to reduce supply voltage. Most low voltage memory arrays use an 8T cell, which has read stability immunity, in order to operate at low voltages. An embodiment of the disclosure determines when a write wordline (WWL) rises. If the determination shows that the WWL has risen, at least one of the plurality of p-channel field effect transistors (pFETS) is disconnected from a voltage supply, and the at least one plurality of n-channel field effect transistors (nFET) passgate transistors are opened.

Abstract translation: 在低功耗CPU中，降低功耗的最佳方法是降低电源电压。 大多数低电压存储器阵列使用具有读稳定性抗扰度的8T电池，以便在低电压下工作。 本公开的实施例确定写入字线（WWL）何时上升。 如果确定显示WWL已经升高，则多个p沟道场效应晶体管（pFETS）中的至少一个与电压源断开，并且至少一个多个n沟道场效应晶体管（nFET）通孔 晶体管被打开。

公开(公告)号：US08976618B1

公开(公告)日：2015-03-10

申请号：US14161530

申请日：2014-01-22

Applicant: QUALCOMM Incorporated

Inventor： Manish Garg ,  Rajesh Kumar

IPC: G11C8/00 ,  G11C8/10 ,  G11C11/412

CPC classification number: G11C8/10 ,  G06F12/0864 ,  G06F12/0895 ,  G06F2212/6082 ,  G11C7/1006 ,  G11C11/412 ,  G11C11/419

Abstract: Decoded 2n-bit bitcells in memory for storing decoded bits, and related systems and methods are disclosed. In one embodiment, a decoded 2n-bit bitcell containing 2n state nodes is provided. Each state node includes storage node to store decoded bit. Storage node provides bit to read bitline, coupled to decoded word output. Each state node includes active decoded bit input coupled to storage node that receives decoded bit from decoded word to store in storage node in response to write wordline. State node comprised of 2n−1 passive decoded bit inputs, each coupled to one of 2n−1 remaining storage nodes. 2n−1 passive decoded bit inputs receive 2n−1 decoded bits not received by active decoded bit input. State node includes logic that receives 2n−1 decoded bits. Logic retains decoded bit, provides it to passive decoded bit output. Passive decoded word output is coupled to storage node to store decoded bit in storage node.

Abstract translation: 公开了用于存储解码比特的存储器中的解码的2n比特单元，以及相关的系统和方法。 在一个实施例中，提供了包含2n个状态节点的解码的2n位比特单元。 每个状态节点包括存储解码位的存储节点。 存储节点提供位读取位线，耦合到解码字输出。 每个状态节点包括耦合到存储节点的活动解码位输入，其响应于写入字线从解码字接收解码位以存储在存储节点中。 状态节点由2n-1个无源解码比特输入组成，每个被耦合到2n-1个剩余存储节点中的一个。 2n-1个无源解码位输入接收未被有效解码位输入接收的2n-1个解码位。 状态节点包括接收2n-1个解码位的逻辑。 逻辑保持解码位，将其提供给无源解码位输出。 无源解码字输出耦合到存储节点以将解码的比特存储在存储节点中。

公开(公告)号：US20130188434A1

公开(公告)日：2013-07-25

申请号：US13746528

申请日：2013-01-22

Applicant: QUALCOMM INCORPORATED

Inventor： Joshua L. Puckett ,  Manish Garg ,  Harish Shankar

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C11/412 ,  G11C11/419

Abstract: In low power CPUs, the best way to reduce power is to reduce supply voltage. Most low voltage memory arrays use an 8T cell, which has read stability immunity, in order to operate at low voltages. An embodiment of the disclosure determines when a write wordline (WWL) rises. If the determination shows that the WWL has risen, at least one of the plurality of p-channel field effect transistors (pFETS) is disconnected from a voltage supply, and the at least one plurality of n-channel field effect transistors (nFET) passe ate transistors are opened.

Abstract translation: 在低功耗CPU中，降低功耗的最佳方法是降低电源电压。 大多数低电压存储器阵列使用具有读稳定性抗扰度的8T电池，以便在低电压下工作。 本公开的实施例确定写入字线（WWL）何时上升。 如果确定表明WWL已经升高，则多个p沟道场效应晶体管（pFETS）中的至少一个与电压源断开，并且至少一个多个n沟道场效应晶体管（nFET）passe 打开晶体管。

公开(公告)号：US11593117B2

公开(公告)日：2023-02-28

申请号：US16024725

申请日：2018-06-29

Applicant: QUALCOMM Incorporated

Inventor： Harsh Thakker ,  Thomas Philip Speier ,  Rodney Wayne Smith ,  Kevin Jaget ,  James Norris Dieffenderfer ,  Michael Morrow ,  Pritha Ghoshal ,  Yusuf Cagatay Tekmen ,  Brian Stempel ,  Sang Hoon Lee ,  Manish Garg

IPC: G06F9/38 ,  G06F9/30

Abstract: Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.

公开(公告)号：US10559352B2

公开(公告)日：2020-02-11

申请号：US16134937

申请日：2018-09-18

Applicant: QUALCOMM Incorporated

Inventor： Harish Shankar ,  Manish Garg ,  Rahul Krishnakumar Nadkarni ,  Rajesh Kumar ,  Michael Phan

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/08 ,  G11C8/18 ,  G11C7/10 ,  G11C11/418

Abstract: A memory system includes a sense amplifier electrically coupled to a first bitline and a second bitline associated with a column of a memory array, a bl transistor electrically coupled to the first bitline, wherein the bl transistor is configured to receive as input a first electrical signal from the first bitline, and a blb transistor electrically coupled to the second bitline, wherein the blb transistor is configured to receive as input a second electrical signal from the second bitline, wherein an output of the bl transistor and an output of the blb transistor are electrically coupled together as a common output, and wherein the sense amplifier is configured to receive as an input the common output of the bl transistor and the blb transistor.

公开(公告)号：US20160359487A1

公开(公告)日：2016-12-08

申请号：US14731747

申请日：2015-06-05

Applicant: QUALCOMM Incorporated

Inventor： Rahul Krishnakumar Nadkarni ,  Stephen Edward Liles ,  Manish Garg

IPC: H03K19/0185

CPC classification number: H03K19/018521 ,  H03K3/012 ,  H03K3/356165

Abstract: Voltage level shifters employing preconditioning circuits are disclosed. Related systems and methods are also disclosed. In one aspect, voltage level shifter is configured to generate a voltage level shifted non-complement output signal and complement output signal corresponding to non-complement input signal and complement input signal, respectively. First pull-up circuit is configured to generate complement output signal in response to non-complement input signal transitioning to logic low voltage. First pull-down circuit is configured to generate non-complement output signal in response to complement input signal transitioning to logic high voltage. First preconditioning circuit is configured to receive non-complement and complement output signals and generate and provide shifted voltage signal to complement output in response to non-complement output signal transitioning to logic low voltage. This allows the complement output signal to transition to the shifted voltage more quickly.

Abstract translation: 公开了采用预处理电路的电压电平移位器。 还公开了相关系统和方法。 一方面，电压电平移位器被配置为分别产生对应于非补码输入信号和补码输入信号的电压电平移位的非补码输出信号和补码输出信号。 第一上拉电路被配置为响应于非补码输入信号转换到逻辑低电压而产生补码输出信号。 第一下拉电路被配置为响应于补充输入信号转换到逻辑高电压而产生非补码输出信号。 第一预处理电路被配置为接收非补码和补码输出信号，并且响应于非补码输出信号转换到逻辑低电压而生成并提供移位电压信号以补码输出。 这允许补码输出信号更快地转换到移位的电压。

公开(公告)号：US09396794B1

公开(公告)日：2016-07-19

申请号：US14827235

申请日：2015-08-14

Applicant: QUALCOMM Incorporated

Inventor： Rahul Nadkarni ,  Manish Garg

IPC: G11C15/00 ,  G11C15/04 ,  G11C11/419

CPC classification number: G11C15/04

Abstract: Systems and methods relate to a matchline receiver of a content-addressable memory (CAM). A matchline of the CAM, which provides a hit/miss indication for a search operation of a data word is provided to the matchline receiver. The matchline receiver comprises a retention circuit to provide a hit/miss output, wherein the retention circuit retains, at the hit/miss output, the hit/miss indication provided by the matchline during a first clock phase of a clock, even if the hit/miss indication provided by the matchline is modified by a write operation or an invalidation operation during the first clock phase.

Abstract translation: 系统和方法涉及内容可寻址存储器（CAM）的匹配线接收器。 为匹配线接收机提供CAM的匹配线，该匹配线为数据字的搜索操作提供命中/未命中指示。 匹配线接收器包括保持电路以提供命中/未命中输出，其中保持电路在命中/未命中输出时保持在时钟的第一时钟阶段期间由匹配线提供的命中/未命中指示，即使命中 在第一时钟阶段期间，通过写操作或无效操作修改由匹配线提供的/未命中指示。