公开(公告)号：US09633996B1

公开(公告)日：2017-04-25

申请号：US15081396

申请日：2016-03-25

Applicant: QUALCOMM Incorporated

Inventor： Lixin Ge ,  P R Chidambaram ,  Haining Yang ,  John Jianhong Zhu ,  Kern Rim

IPC: H01L27/06 ,  H01L29/78 ,  H01L29/06 ,  H01L49/02 ,  H01L29/94 ,  H01L29/66 ,  H01L27/07

CPC classification number: H01L27/0629 ,  H01L27/0716 ,  H01L27/11582 ,  H01L28/00 ,  H01L28/24 ,  H01L29/0653 ,  H01L29/66181 ,  H01L29/7851 ,  H01L29/94

Abstract: A semiconductor device arranged between a source voltage (Vss) and a power voltage (Vdd) may include a first terminal coupled to the power voltage Vdd. The semiconductor device may also include a decoupling capacitor. The decoupling capacitor may include a semiconductor fin coupled to the first terminal, a dielectric layer on the semiconductor fin, and a gate on the dielectric layer. The semiconductor device may further include a second terminal. The second terminal may include a conductive gate resistor coupled in series with the gate of the decoupling capacitor. The second terminal may be coupled to the source voltage Vss via a first interconnect layer (M1).

公开(公告)号：US20140203404A1

公开(公告)日：2014-07-24

申请号：US13745962

申请日：2013-01-21

Applicant: QUALCOMM INCORPORATED

Inventor： Jihong Choi ,  John J. Zhu ,  PR Chidambaram ,  Bin Yang ,  Lixin Ge

IPC: H01L49/02

CPC classification number: H01L28/87 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Spiral metal-on-metal (MoM or SMoM) capacitors and related systems and methods of forming MoM capacitors are disclosed. In one embodiment, a MoM capacitor disposed in a semiconductor die is disclosed. The MoM capacitor comprises a first electrode coupled to a first trace. The first trace is coiled in a first inwardly spiraling pattern and comprised of first parallel trace segments. The MoM capacitor also comprises a second electrode coupled to a second trace. The second trace is coiled in the first inwardly spiraling pattern and comprised of second parallel trace segments interdisposed between the first parallel trace segments. Reduced variations in the capacitance allow circuit designers to build circuits with tighter tolerances and generally improve circuit reliability.

Abstract translation: 公开了形成MoM电容器的螺旋金属金属（MoM或SMoM）电容器及相关系统和方法。 在一个实施例中，公开了一种设置在半导体管芯中的MoM电容器。 MoM电容器包括耦合到第一迹线的第一电极。 第一迹线卷绕在第一向内螺旋形的图案中并由第一平行迹线段组成。 MoM电容器还包括耦合到第二迹线的第二电极。 第二迹线卷绕在第一向内螺旋形图案中，并且包括间隔在第一平行迹线段之间的第二平行迹线段。 降低电容的变化允许电路设计者构建更严格公差的电路，并且通常提高电路的可靠性。

公开(公告)号：US20140197519A1

公开(公告)日：2014-07-17

申请号：US13743388

申请日：2013-01-17

Applicant: QUALCOMM INCORPORATED

Inventor： Jihong Choi ,  John J. Zhu ,  PR Chidambaram ,  Bin Yang ,  Lixin Ge

IPC: H01L49/02 ,  G06F17/50

CPC classification number: H01L28/92

Abstract: In a particular embodiment, a method of forming a metal-insulator-metal (MIM) capacitor includes removing, using a lithographic mask, a first portion of an optical planarization layer to expose a region in which the MIM capacitor is to be formed. A second portion of an insulating layer is formed on a first conductive layer that is formed on a plurality of trench surfaces within the region. The method further includes removing at least a third portion of the insulating layer according to a lift-off technique.

Abstract translation: 在特定实施例中，形成金属 - 绝缘体 - 金属（MIM）电容器的方法包括使用光刻掩模去除光学平坦化层的第一部分以暴露其中将形成MIM电容器的区域。 绝缘层的第二部分形成在形成在该区域内的多个沟槽表面上的第一导电层上。 该方法还包括根据剥离技术去除绝缘层的至少第三部分。

公开(公告)号：US20130320494A1

公开(公告)日：2013-12-05

申请号：US13721089

申请日：2012-12-20

Applicant: QUALCOMM INCORPORATED

Inventor： John J. Zhu ,  PR Chidambaram ,  Lixin Ge ,  Bin Yang ,  Jihong Choi

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L27/0207 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor die having a plurality of metal layers, including a set of metal layers having a preferred direction for minimum feature size. The set of metal layers are such that adjacent metal layers have preferred directions orthogonal to one another. Finger capacitors formed in the set of metal layers are such that a finger capacitor formed in one metal layer has a finger direction parallel to the preferred direction of that metal layer. In bidirectional metal layers, capacitor fingers may be in either direction.

Abstract translation: 一种具有多个金属层的半导体管芯，包括一组具有最小特征尺寸的优选方向的金属层。 金属层的组合使得相邻的金属层具有彼此正交的优选方向。 形成在金属层组中的手指电容器使得形成在一个金属层中的手指电容器具有平行于该金属层的优选方向的手指方向。 在双向金属层中，电容指可以在任一方向上。

公开(公告)号：US11973020B2

公开(公告)日：2024-04-30

申请号：US17470274

申请日：2021-09-09

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Lixin Ge ,  Giridhar Nallapati

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/76838 ,  H01L28/40

Abstract: Disclosed are examples of a device and method of fabricating a device including a first top contact, a second top contact, adjacent the first top contact, a first mesa disposed below the first top contact and a second mesa disposed below the second top contact. A first plate of a metal-insulator-metal (MIM) capacitor is disposed below the first top contact and electrically coupled to the first top contact. A first insulator of the MIM capacitor is disposed on the first plate. A second plate of the MIM capacitor is disposed on the first insulator and electrically coupled to the second top contact. A second insulator of the MIM capacitor is disposed on the second plate. A third plate of the MIM capacitor is disposed on the second insulator and electrically coupled to the first top contact.

公开(公告)号：US10756085B2

公开(公告)日：2020-08-25

申请号：US15835810

申请日：2017-12-08

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Bin Yang ,  Lixin Ge

IPC: H01L27/088 ,  H01L27/06 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/762 ,  H03K19/0185 ,  H01L21/8234 ,  G06F30/398 ,  H01L27/092

Abstract: An integrated circuit may include a substrate, a first three-dimensional (3D) transistor formed on a first diffusion region of the substrate, and a second 3D transistor formed on a second diffusion region of the substrate. The first 3D transistor may include a gate that extends from between a source and a drain of the first 3D transistor, across an isolation region of the substrate, to and between a source and a drain of the second 3D transistor. The gate may include a gate metal that has an isolation portion extending over the isolation region of the substrate and a diffusion portion extending over the first and second diffusion regions of the substrate. The isolation portion of the gate metal has a thickness less than a maximum thickness of the diffusion portion of the gate metal.

公开(公告)号：US10714582B2

公开(公告)日：2020-07-14

申请号：US16002459

申请日：2018-06-07

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Ye Lu ,  Lixin Ge

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  G11C11/22 ,  H01L29/423 ,  H01L29/49

Abstract: A Field-Effect Transistor (FET) with a negative capacitance layer to increase power density provides a negative capacitor connected in series with a conventional positive capacitor. The dimensions of the negative capacitor are controlled to allow the difference in capacitances between the negative capacitor and the positive capacitor to approach zero, which in turn provides a large total capacitance. The large total capacitance provides for increased power density.

公开(公告)号：US10665678B2

公开(公告)日：2020-05-26

申请号：US16288558

申请日：2019-02-28

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Junjing Bao ,  Bin Yang ,  Lixin Ge ,  Yun Yue

IPC: H01L21/02 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/72

Abstract: An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.

公开(公告)号：US20190195700A1

公开(公告)日：2019-06-27

申请号：US16268669

申请日：2019-02-06

Applicant: QUALCOMM Incorporated

Inventor： Lixin Ge ,  Periannan Chidambaram ,  Bin Yang ,  Jiefeng Jeff Lin ,  Giridhar Nallapati ,  Bo Yu ,  Jie Deng ,  Jun Yuan ,  Stanley Seungchul Song

IPC: G01K7/01 ,  H01L23/522 ,  H01L23/34 ,  G01K7/18 ,  H01L49/02 ,  G01K7/24 ,  H01L21/768 ,  H01L21/3213 ,  H01L23/528 ,  H01L21/66

CPC classification number: G01K7/01 ,  G01K7/186 ,  G01K7/24 ,  H01L21/32139 ,  H01L21/76895 ,  H01L22/34 ,  H01L23/34 ,  H01L23/5228 ,  H01L23/528 ,  H01L27/0629 ,  H01L28/24

Abstract: Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC adjacent to an active semiconductor area to sense ambient temperature in the adjacent active semiconductor area. Voltage of the metal resistor will change as a function of ambient temperature of the metal resistor, which can be sensed to measure the ambient temperature around devices in the active semiconductor layer adjacent to the metal resistor. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized adjacent and close to semiconductor devices to more accurately sense ambient temperature of the semiconductor devices. The same fabrication processes used to create contacts in the MOL layer can be used to fabricate the metal resistor.

公开(公告)号：US10263080B2

公开(公告)日：2019-04-16

申请号：US15672017

申请日：2017-08-08

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Junjing Bao ,  Bin Yang ,  Lixin Ge ,  Yun Yue

IPC: H01L29/66 ,  H01L29/16 ,  H01L21/02 ,  H01L29/10 ,  H01L29/72 ,  H01L29/78

Abstract: An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.