公开(公告)号：US20160035622A1

公开(公告)日：2016-02-04

申请号：US14447399

申请日：2014-07-30

Applicant: QUALCOMM Incorporated

Inventor： Rajneesh Kumar ,  Houssam Wafic Jomaa ,  David Fraser Rae ,  Layal Rouhana ,  Omar James Bchir

IPC: H01L21/768 ,  H01L21/48 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76852 ,  H01L21/4825 ,  H01L21/76879 ,  H01L23/4952 ,  H01L23/49527 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/528 ,  H01L23/53204 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/00014

Abstract: Some features pertain to an integrated device that includes a first substrate, a first solder resist layer coupled to the first substrate, a second solder resist layer coupled to the first solder resist layer, and an opening in the first and second solder resist layers, the opening comprising a sidewall completely covered with the second solder resist layer, where a sidewall of the second solder resist layer covers a sidewall of the first solder resist layer. In some implementations, the opening is at least partially filled with an electrically conductive material. The electrically conductive material includes one of solder and/or an interconnect. The integrated device includes a first interconnect coupled to the electrically conductive material. The first interconnect is one of at least a solder, and/or an interconnect ball. In some implementations, the integrated device includes a pad coupled to the substrate, and a first interconnect coupled to the pad.

Abstract translation: 一些特征涉及集成器件，其包括第一衬底，耦合到第一衬底的第一阻焊层，耦合到第一阻焊层的第二阻焊层和第一和第二阻焊层中的开口， 开口，其包括完全被第二阻焊层覆盖的侧壁，其中第二阻焊层的侧壁覆盖第一阻焊层的侧壁。 在一些实施方案中，开口至少部分地填充有导电材料。 导电材料包括焊料和/或互连中的一种。 集成器件包括耦合到导电材料的第一互连。 第一互连是至少焊料和/或互连球之一。 在一些实施方案中，集成器件包括耦合到衬底的焊盘和耦合到焊盘的第一互连。

公开(公告)号：US20210280523A1

公开(公告)日：2021-09-09

申请号：US16916339

申请日：2020-06-30

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Aniket Patil ,  Marcus Hsu ,  David Fraser Rae

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: Integrated circuit (IC) packages employing split, double-sided IC metallization structures to facilitate a semiconductor die (“IC die”) module employing stacked dice, and related fabrication methods are disclosed. Multiple IC dice in the IC package are stacked and bonded together in a back-to-back, top and bottom IC die configuration in an IC die module, which can minimize the overall height of the IC package. The metallization structure is split between separate top and bottom metallization structures adjacent to respective top and bottom surfaces of the IC die module to facilitate die-to-die and external electrical connections to the dice. The top and bottom metallization structures can be double-sided by exposing substrate interconnects on respective inner and outer surfaces for respective die and external electrical interconnections. In other exemplary aspects, the top and bottom metallization structures can include redistribution layers (RDLs) to provide increased electrical conductivity between die interconnects and substrate interconnects.

公开(公告)号：US10163687B2

公开(公告)日：2018-12-25

申请号：US14861484

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： David Fraser Rae ,  Lizabeth Ann Keser ,  Reynante Tamunan Alvarado

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/16 ,  H01L21/768 ,  H01L23/498 ,  H01L23/538 ,  H01L21/00

Abstract: A package may include a die proximate to a structure having a substrate with interconnects and a first component coupled to the interconnects. The die may be face up or face down. The package may include a first redistribution layer coupling the die to the interconnects of the structure and a mold compound covering the die and maybe the structure.

公开(公告)号：US09985010B2

公开(公告)日：2018-05-29

申请号：US14859316

申请日：2015-09-20

Applicant: QUALCOMM Incorporated

Inventor： David Fraser Rae ,  Lizabeth Ann Keser ,  Reynante Tamunan Alvarado

IPC: H01L23/538 ,  H01L25/16 ,  H01L21/311 ,  H01L21/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/16 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/75 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2224/83

Abstract: An integrated package may be manufactured in a die face up orientation with a component proximate to the attached die by creating a cavity in the mold compound during fabrication. The cavity is created with an adhesive layer on the bottom to hold a component such that the top surface of the component is co-planar with the top surface of the attached die. This may allow backside grinding to take place that will not damage the component because the top surface alignment between the attached die and the component prevents the depth of the cavity from extending into the portion of the package that is ground away.

公开(公告)号：US09601472B2

公开(公告)日：2017-03-21

申请号：US14837917

申请日：2015-08-27

Applicant: QUALCOMM Incorporated

Inventor： Lizabeth Ann Keser ,  David Fraser Rae

IPC: H01L25/10 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/105 ,  H01L21/568 ,  H01L23/13 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Some features pertain to a package on package (PoP) device that includes a first package, a first solder interconnect coupled to the first integrated circuit package, and a second package coupled to the first package through the first solder interconnect. The second package includes a first die, a package interconnect comprising a first pad, where the first solder interconnect is coupled to the first pad of the package interconnect. The second package also includes a redistribution portion coupled to the first die and the package interconnect, an encapsulation layer at least partially encapsulating the first die and the package interconnect. The first pad may include a surface that has low roughness. The encapsulation layer may encapsulate the package interconnect such that the encapsulation layer encapsulates at least a portion of the first solder interconnect.

公开(公告)号：US20160372446A1

公开(公告)日：2016-12-22

申请号：US14811261

申请日：2015-07-28

Applicant: QUALCOMM Incorporated

Inventor： Lizabeth Ann Keser ,  David Fraser Rae ,  Piyush Gupta

IPC: H01L25/065 ,  H01L25/00 ,  H01L25/18 ,  H01L23/31 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/31116 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76802 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/03 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/43 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/89 ,  H01L24/96 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/08245 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/48471 ,  H01L2224/49107 ,  H01L2224/49109 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/8538 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06579 ,  H01L2924/00014 ,  H01L2924/12 ,  H01L2924/1304 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/32245 ,  H01L2224/48247

Abstract: An integrated circuit (IC) package that includes a first die, a wire bond coupled to the first die, a first encapsulation layer that at least partially encapsulates the first die and the wire bond, a second die, a redistribution portion coupled to the second die, and a second encapsulation layer that at least partially encapsulates the second die. In some implementations, the wire bond is coupled to the redistribution portion. In some implementations, the integrated circuit (IC) package further includes a package interconnect that is at least partially encapsulated by the second encapsulation layer. In some implementations, the integrated circuit (IC) package further includes a via that is at least partially encapsulated by the second encapsulation layer. In some implementations, the integrated circuit (IC) package has a height of about 500 microns (μm) or less.

Abstract translation: 一种集成电路（IC）封装，其包括第一管芯，耦合到所述第一管芯的引线接合，至少部分地封装所述第一管芯和所述引线接合的第一封装层，第二管芯，耦合到所述第二管芯的再分配部分 并且至少部分地封装第二管芯的第二封装层。 在一些实施方式中，引线接合耦合到再分配部分。 在一些实现中，集成电路（IC）封装进一步包括由第二封装层至少部分封装的封装互连。 在一些实现中，集成电路（IC）封装还包括至少部分地由第二封装层封装的通孔。 在一些实现中，集成电路（IC）封装具有约500微米（μm）或更小的高度。

公开(公告)号：US09355898B2

公开(公告)日：2016-05-31

申请号：US14447399

申请日：2014-07-30

Applicant: QUALCOMM Incorporated

Inventor： Rajneesh Kumar ,  Houssam Wafic Jomaa ,  David Fraser Rae ,  Layal Rouhana ,  Omar James Bchir

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/495 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L21/76852 ,  H01L21/4825 ,  H01L21/76879 ,  H01L23/4952 ,  H01L23/49527 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/528 ,  H01L23/53204 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/00014

Abstract: Some features pertain to an integrated device that includes a first substrate, a first solder resist layer coupled to the first substrate, a second solder resist layer coupled to the first solder resist layer, and an opening in the first and second solder resist layers, the opening comprising a sidewall completely covered with the second solder resist layer, where a sidewall of the second solder resist layer covers a sidewall of the first solder resist layer. In some implementations, the opening is at least partially filled with an electrically conductive material. The electrically conductive material includes one of solder and/or an interconnect. The integrated device includes a first interconnect coupled to the electrically conductive material. The first interconnect is one of at least a solder, and/or an interconnect ball. In some implementations, the integrated device includes a pad coupled to the substrate, and a first interconnect coupled to the pad.

Abstract translation: 一些特征涉及集成器件，其包括第一衬底，耦合到第一衬底的第一阻焊层，耦合到第一阻焊层的第二阻焊层和第一和第二阻焊层中的开口， 开口，其包括完全被第二阻焊层覆盖的侧壁，其中第二阻焊层的侧壁覆盖第一阻焊层的侧壁。 在一些实施方案中，开口至少部分地填充有导电材料。 导电材料包括焊料和/或互连中的一种。 集成器件包括耦合到导电材料的第一互连。 第一互连是至少焊料和/或互连球之一。 在一些实施方案中，集成器件包括耦合到衬底的焊盘和耦合到焊盘的第一互连。