公开(公告)号：US20150111341A1

公开(公告)日：2015-04-23

申请号：US14149882

申请日：2014-01-08

Applicant: QUALCOMM Incorporated

Inventor： Yong Ju Lee ,  Yang Du

IPC: H01L21/268 ,  H01L21/324

CPC classification number: H01L21/268 ,  H01L21/324 ,  H01L21/8221 ,  H01L27/0688

Abstract: Laser annealing methods for integrated circuits (IC) are disclosed. In particular, an upper surface of an integrated circuit is annealed with a laser using a brief burst of light from the laser. In an exemplary embodiment, the brief burst of light from the laser lasts approximately fifty (50) to five hundred (500) microseconds. This brief burst will raise the temperature of the surface to approximately 1200° C.

Abstract translation: 公开了集成电路（IC）的激光退火方法。 特别地，使用来自激光器的短暂的光源，使用激光器对集成电路的上表面进行退火。 在示例性实施例中，来自激光器的短暂的光脉冲持续大约五十（50）至五百（500）微秒。 这种短暂的爆发会使表面的温度升高到大约1200℃

公开(公告)号：US20150022250A1

公开(公告)日：2015-01-22

申请号：US14012445

申请日：2013-08-28

Applicant: Qualcomm Incorporated

Inventor： Pratyush Kamal ,  Yang Du

IPC: H03K3/037 ,  G06F17/50

CPC classification number: H03K3/0372 ,  G06F17/5068 ,  H01L27/0688 ,  H03K3/35625

Abstract: Monolithic three dimensional (3D) flip-flops with minimal clock skew and related systems and methods are disclosed. The present disclosure provides a 3D integrated circuit (IC) (3DIC) that has a flop spread across at least two tiers of the 3DIC. The flop is split across tiers with transistor partitioning in such a way that keeps all the clock related devices at the same tier, thus potentially giving better setup, hold and clock-to-q margin. In particular, a first tier of the 3DIC has the master latch, slave latch, and clock circuit. A second tier has the input circuit and the output circuit.

Abstract translation: 公开了具有最小时钟偏移和相关系统和方法的单片三维（3D）触发器。 本公开提供了具有翻转的3D集成电路（3DIC）（3DIC），其跨越3DIC的至少两层。 触发器分为跨级别，晶体管分区，使得所有与时钟相关的器件保持在同一层级，从而可能提供更好的设置，保持和时钟到余裕。 特别地，3DIC的第一层具有主锁存器，从锁存器和时钟电路。 第二层有输入电路和输出电路。

公开(公告)号：US20130082235A1

公开(公告)日：2013-04-04

申请号：US13644720

申请日：2012-10-04

Applicant: Qualcomm Incorporated

Inventor： Shiqun Gu ,  Yang Du

IPC: H01L27/04 ,  H01L21/50 ,  B82Y99/00

CPC classification number: H01L27/0688 ,  H01L21/2007 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/1606

Abstract: A monolithic three dimensional integrated circuit device includes a first layer having first active devices. The monolithic three dimensional integrated circuit device also includes a second layer having second active devices that each include a graphene portion. The second layer can be fabricated on the first layer to form a stack of active devices. A base substrate may support the stack of active devices.

Abstract translation: 单片三维集成电路器件包括具有第一有源器件的第一层。 单片三维集成电路器件还包括具有第二有源器件的第二层，每个有源器件均包括石墨烯部分。 可以在第一层上制造第二层以形成有源器件的堆叠。 基底可以支撑有源器件的堆叠。

公开(公告)号：US20190122973A1

公开(公告)日：2019-04-25

申请号：US16220764

申请日：2018-12-14

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Shreepad Amar Panth ,  Yang Du ,  Robert Philip Gilmore

IPC: H01L23/498 ,  G06F17/50 ,  H01L21/768

CPC classification number: H01L23/49827 ,  G06F17/5068 ,  H01L21/76802 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to the bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

公开(公告)号：US09929733B1

公开(公告)日：2018-03-27

申请号：US15437871

申请日：2017-02-21

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Kambiz Samadi ,  Jing Xie ,  Yang Du

IPC: H01L23/522 ,  H03K19/094 ,  H01L23/528 ,  H01L27/06 ,  H01L27/118

CPC classification number: H03K19/094 ,  G06F17/505 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/11807 ,  H01L2027/11851 ,  H01L2027/11872 ,  H01L2027/11875

Abstract: A 3D integrated circuit reduces delay when a signal traverses logical blocks of the integrated circuit. In one instance, the 3D integrated circuit has a first tier and a second tier including one or more first and second logical blocks, respectively. The first logical block(s) include a first primary output logic gate, a first primary input logic gate, a first primary input pin and a first primary output pin. The first primary output pin lies within a perimeter defined by a total area occupied by logic gates of the first logical block(s). The second logical block(s) include a second primary output logic gate, a second primary input logic gate, a second primary input pin and a second primary output pin. The second primary input pin is coupled to the first primary output pin.

公开(公告)号：US09418985B2

公开(公告)日：2016-08-16

申请号：US14013399

申请日：2013-08-29

Applicant: QUALCOMM Incorporated

Inventor： Yang Du

IPC: H04Q9/00 ,  H01L27/06 ,  H01L21/77 ,  H01L21/822 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L21/77 ,  H01L21/8221 ,  H01L23/481 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2225/06544 ,  Y10T29/41 ,  H01L2924/00014

Abstract: Embodiments disclosed in the detailed description include a complete system-on-chip (SOC) solution using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) integration technology. The present disclosure includes example of the ability to customize layers within a monolithic 3DIC and the accompanying short interconnections possible between tiers through monolithic intertier vias (MIV) to create a system on a chip. In particular, different tiers of the 3DIC are constructed to support different functionality and comply with differing design criteria. Thus, the 3DIC can have an analog layer, layers with higher voltage threshold, layers with lower leakage current, layers of different material to implement components that need different base materials and the like. Unlike the stacked dies, the upper layers may be the same size as the lower layers because no external wiring connections are required.

Abstract translation: 在详细描述中公开的实施例包括使用单片三维（3D）集成电路（IC）（3DIC）（3DIC）集成技术的完整的片上系统（SOC）解决方案。 本公开包括定制单片3DIC内的层的能力的示例以及通过整体式层间通孔（MIV）在层之间可能的伴随的短互连以在芯片上创建系统的示例。 特别地，3DIC的不同层被构造成支持不同的功能并且符合不同的设计标准。 因此，3DIC可以具有模拟层，具有较高电压阈值的层，具有较低漏电流的层，不同材料层，以实现需要不同基底材料等的部件。 与堆叠的模具不同，上层可以与下层具有相同的尺寸，因为不需要外部布线连接。

公开(公告)号：US20150333005A1

公开(公告)日：2015-11-19

申请号：US14795914

申请日：2015-07-10

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Shreepad Amar Panth ,  Pratyush Kamal ,  Yang Du

IPC: H01L23/522 ,  G06F17/50 ,  H01L27/06

CPC classification number: H01L23/5226 ,  G06F17/5072 ,  G06F17/5081 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Placement of Monolithic Inter-tier Vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace is disclosed. In one embodiment, a method of placing MIVs in a monolithic 3DIC using clustering is provided. The method comprises determining if any MIV placement clusters are included within a plurality of initial MIV placements of a plurality of MIVs within an initial 3DIC layout plan. The method further comprises aligning each MIV of the plurality of MIVs within each MIV placement cluster in the initial 3DIC layout plan at a final MIV placement for each MIV placement cluster to provide a clustered 3DIC layout plan.

Abstract translation: 公开了使用聚类来增加可用空白位置的单片三维（3D）集成电路（IC）（3DIC）中的单片间通道（MIV））。 在一个实施例中，提供了使用聚类将MIV放置在单片3DIC中的方法。 该方法包括确定在初始3DIC布局图中是否有多个MIV的多个初始MIV布置内是否包括任何MIV布局群集。 该方法还包括在初始3DIC布局图中的每个MIV放置簇内的多个MIV中的每个MIV在每个MIV放置簇的最终MIV放置处对齐以提供聚集的3DIC布局图。

公开(公告)号：US20150311138A1

公开(公告)日：2015-10-29

申请号：US14264229

申请日：2014-04-29

Applicant: QUALCOMM Incorporated

Inventor： Yong Ju Lee ,  Yang Du

IPC: H01L23/373 ,  H01L29/51 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L23/367 ,  H01L23/3731 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/517 ,  H01L29/518 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Transistors with improved thermal conductivity are disclosed. Portions of the transistor or elements adjacent to the transistor are made from materials that are electrically insulative, but have high thermal conductivities. Increased thermal conductivity provides increased heat dissipation from the transistor, which results in less resistance and less power consumption, which in turns generally improves performance. For example, in a first non-limiting exemplary aspect, the material that can be included for electrical insulation, but having high thermal conductivity for increased heat dissipation is Beryllium Oxide (BeO). In a second non-limiting exemplary aspect, the material that can be included for electrical insulation, but having high thermal conductivity for increased heat dissipation is Aluminum Nitride (AlN).

Abstract translation: 公开了具有改善的热导率的晶体管。 与晶体管相邻的晶体管或元件的部分由电绝缘但具有高导热性的材料制成。 增加的热导率提高了晶体管的散热，这导致较少的电阻和更少的功耗，而这通常会改善性能。 例如，在第一非限制性示例性方面，可以包括用于电绝缘但具有高热导率以增加散热的材料是氧化铍（BeO）。 在第二非限制性示例性方面，可以包括用于电绝缘但具有高导热性以增加散热的材料是氮化铝（AlN）。

公开(公告)号：US09171608B2

公开(公告)日：2015-10-27

申请号：US13939274

申请日：2013-07-11

Applicant: QUALCOMM Incorporated

Inventor： Jing Xie ,  Yang Du

IPC: G11C5/06 ,  G11C11/412 ,  G11C5/02 ,  H01L27/06 ,  H01L27/11

CPC classification number: G11C11/412 ,  G11C5/025 ,  G11C11/419 ,  H01L21/768 ,  H01L23/481 ,  H01L23/5226 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) (3DIC) tiers is disclosed. Related 3DICs, 3DIC processor cores, and methods are also disclosed. In embodiments disclosed herein, memory read access ports of a memory block are separated from a memory cell in different tiers of a 3DIC. 3DICs achieve higher device packing density, lower interconnect delays, and lower costs. In this manner, different supply voltages can be provided for the read access ports and the memory cell to be able to lower supply voltage for the read access ports. Static noise margins and read/write noise margins in the memory cell may be provided as a result. Providing multiple power supply rails inside a non-separated memory block that increases area can also be avoided.

Abstract translation: 公开了3D集成电路（IC）（3DIC）层中的三维（3D）存储单元分离。 还公开了相关3DIC，3DIC处理器核心和方法。 在本文公开的实施例中，存储器块的存储器读取访问端口与3DIC的不同层级的存储器单元分离。 3DIC实现更高的器件封装密度，更低的互连延迟和更低的成本。 以这种方式，可以为读访问端口和存储单元提供不同的电源电压，以便能够降低读访问端口的电源电压。 结果可能会提供存储单元中的静态噪声容限和读/写噪声余量。 还可以避免增加面积的非分开的存储块内的多个电源轨。

公开(公告)号：US09076953B2

公开(公告)日：2015-07-07

申请号：US13746011

申请日：2013-01-21

Applicant: QUALCOMM Incorporated

Inventor： Yang Du

IPC: H01L29/66 ,  H01L29/84 ,  H01L21/76 ,  G11C11/00 ,  G11C11/14 ,  H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08

CPC classification number: H01L43/02 ,  H01L27/228 ,  H01L29/66984 ,  H01L43/08 ,  H01L43/12

Abstract: Spin transistors and related memory, memory systems, and methods are disclosed. A spin transistor is provided by at least two magnetic tunnel junctions (MTJs) with a shared multiferroic layer. The multiferroic layer is formed from a piezoelectric (PE) thin film over a ferromagnetic thin film (FM channel) with a metal electrode (metal). The ferromagnetic layer functions as the spin channel and the piezoelectric layer is used for transferring piezoelectric stress to control the spin state of the channel. The MTJ on one side of the shared layer forms a source and the MTJ on the other side is a drain for the spin transistor.

Abstract translation: 公开了旋转晶体管和相关存储器，存储器系统和方法。 自旋晶体管由具有共享多铁层的至少两个磁性隧道结（MTJ）提供。 多铁层由金属电极（金属）的铁磁薄膜（FM通道）上的压电（PE）薄膜形成。 铁磁层用作自旋通道，压电层用于转移压电应力以控制通道的自旋状态。 共享层一侧的MTJ形成源极，另一侧的MTJ是自旋晶体管的漏极。