知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

27 records (took 0.049 seconds)

    STATIC RANDOM ACCESS MEMORIES (SRAM) WITH READ-PREFERRED CELL STRUCTURES, WRITE DRIVERS, RELATED SYSTEMS, AND METHODS
    12.
    发明申请
    STATIC RANDOM ACCESS MEMORIES (SRAM) WITH READ-PREFERRED CELL STRUCTURES, WRITE DRIVERS, RELATED SYSTEMS, AND METHODS 有权
    静态随机存取存储器（SRAM），具有读取优先级的单元结构，写驱动程序，相关系统和方法

    公开(公告)号：US20140211546A1

    公开(公告)日：2014-07-31

    申请号：US13869110

    申请日：2013-04-24

    Applicant: Industry-Academic Cooperation Foundation, Yonsei University ,  QUALCOMM INCORPORATED

    Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Bin Yang ,  Zhongze Wang ,  Choh fei Yeap

    IPC: G11C11/412

    CPC classification number: G11C11/412 ,  G11C11/417 ,  G11C11/419 ,  H01L27/0207 ,  H01L27/1104 ,  Y10T29/41

    Abstract: Static random access memories (SRAM) with read-preferred cell structures and write drivers are disclosed. In one embodiment, the SRAM has a six transistor bit cell. The read-preferred bit cell is implemented by providing two inverters, each having a pull up transistor, a pull down transistor and a pass gate transistor. Each pull up transistor is associated with a feedback loop. The feedback loop improves random static noise margin. Each transistor has a width and a length. The lengths of the pass gate transistors are increased. The widths of the pull down transistors are equal to one another and also equal to the widths of the pass gate transistors. The widths of the pass gate and pull down transistors may also be increased relative to prior designs. A write assist circuit may also be used to improve performance.

    Abstract translation: 公开了具有读优选单元结构和写驱动器的静态随机存取存储器（SRAM）。 在一个实施例中，SRAM具有六个晶体管位单元。 读优选位单元通过提供两个反相器来实现，每个反相器具有上拉晶体管，下拉晶体管和通过栅极晶体管。 每个上拉晶体管与反馈回路相关联。 反馈环路改善了随机的静态噪声容限。 每个晶体管具有宽度和长度。 传输栅晶体管的长度增加。 下拉晶体管的宽度彼此相等，并且也等于通过栅极晶体管的宽度。 通过栅极和下拉晶体管的宽度也可以相对于现有设计而增加。 也可以使用写辅助电路来提高性能。

    Latching circuit
    13.
    发明授权
    Latching circuit 有权
    闭锁电路

    公开(公告)号：US08717811B2

    公开(公告)日：2014-05-06

    申请号：US13785338

    申请日：2013-03-05

    Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

    Inventor： Seong-Ook Jung ,  Kyungho Ryu ,  Jisu Kim ,  Jung Pill Kim ,  Seung H. Kang

    IPC: G11C11/00

    CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0002 ,  G11C14/009

    Abstract: A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the resistance-based memory element at a first operating point of the sensing circuit.

    Abstract translation: 非易失性锁存电路包括一对交叉耦合的反相器，一对基于电阻的存储器元件和被配置为将数据写入到该对基于电阻的存储器元件的写入电路。 在锁定操作期间，一对基于电阻的存储器元件与一对交叉耦合的反相器隔离。 感测电路包括第一电流路径，其包括基于电阻的存储元件和感测电路的输出。 感测电路包括第二电流路径，以减小在感测电路的第一工作点处通过基于电阻的存储元件的电流。

    DUAL WRITE WORDLINE MEMORY CELL
    16.
    发明申请
    DUAL WRITE WORDLINE MEMORY CELL 有权
    双写WORDLINE MEMORY CELL

    公开(公告)号：US20150380080A1

    公开(公告)日：2015-12-31

    申请号：US14320024

    申请日：2014-06-30

    Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

    Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Stanley Seungchul Song ,  Choh Fei Yeap ,  Zhongze Wang

    IPC: G11C11/419 ,  G11C5/06

    CPC classification number: G11C11/419 ,  G11C5/02 ,  G11C7/00 ,  G11C7/20 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/417

    Abstract: A static random-access memory (SRAM) memory cell includes a pair of cross-coupled inverters and a gating transistor coupled to a first node of a first inverter of the pair of cross-coupled inverters. A gate of the gating transistor is coupled to a first wordline. The gating transistor is configured to selectively couple a bitline to the first node of the first inverter responsive to a first wordline signal. The first inverter has a second node coupled to a second wordline. The first wordline and the second wordline are each independently controllable.

    Abstract translation: 静态随机存取存储器（SRAM）存储单元包括一对交叉耦合的反相器和耦合到该对交叉耦合的反相器的第一反相器的第一节点的选通晶体管。 门控晶体管的栅极耦合到第一字线。 门控晶体管被配置为响应于第一字线信号而选择性地将位线耦合到第一逆变器的第一节点。 第一反相器具有耦合到第二字线的第二节点。 第一个字线和第二个字线都是独立可控的。

    NMOS-offset canceling current-latched sense amplifier
    17.
    发明授权
    NMOS-offset canceling current-latched sense amplifier 有权
    NMOS偏移消除电流锁存读出放大器

    公开(公告)号：US09111623B1

    公开(公告)日：2015-08-18

    申请号：US14179115

    申请日：2014-02-12

    Applicant: QUALCOMM INCORPORATED ,  Industry-Academic Cooperation Foundation, Yonsei University

    Inventor： Seong-Ook Jung ,  Taehui Na ,  Ji-su Kim ,  Jung Pill Kim ,  Seung Hyuk Kang

    IPC: G11C11/16

    CPC classification number: G11C11/1673 ,  G11C7/02 ,  G11C7/065 ,  G11C7/08 ,  G11C11/1693 ,  G11C13/004 ,  G11C2013/0054

    Abstract: A resistive memory sensing method includes sensing outputs of an offset-cancelling dual stage sensing circuit (OCDS-SC) by an NMOS offset-cancelling current latched sense amplifier circuit (NOC-CLSA). The NOC-CLSA is configured with a reduced input capacitance and a reduced offset voltage. Input transistors of the NOC-CLSA are coupled between latch circuitry and ground. A first phase output of the OCDS-SC is stored by the NOC-CLSA during a pre-charge step of the NOC-CLSA operation. A second phase output of the OCDS-SC is stored by the NOC-CLSA during an offset-cancelling step of the NOC-CLSA operation. By pipelining the OCDS-SC and NOC-CLSA, a sensing delay penalty of the OCDS-SC is overcome.

    Abstract translation: 电阻式存储器感测方法包括通过NMOS偏移消除电流锁存读出放大器电路（NOC-CLSA）来感测偏移消除双级感测电路（OCDS-SC）的输出。 NOC-CLSA配置有降低的输入电容和降低的失调电压。 NOC-CLSA的输入晶体管耦合在锁存电路和地之间。 在NOC-CLSA操作的预充电步骤期间，OCDS-SC的第一相输出由NOC-CLSA存储。 在NOC-CLSA操作的偏移消除步骤期间，OCDS-SC的第二相输出由NOC-CLSA存储。 通过流水线OCDS-SC和NOC-CLSA，克服了OCDS-SC的感测延迟损失。

    SYSTEM AND METHOD OF SENSING A MEMORY CELL
    18.
    发明申请
    SYSTEM AND METHOD OF SENSING A MEMORY CELL 有权
    感知记忆细胞的系统和方法

    公开(公告)号：US20140269031A1

    公开(公告)日：2014-09-18

    申请号：US13835251

    申请日：2013-03-15

    Applicant: QUALCOMM INCORPORATED ,  Industry-Academic Cooperation Foundation, Yonsei

    Inventor： Seong-Ook Jung ,  Taehui Na ,  Jisu Kim ,  Seung H. Kang ,  Jung Pill Kim

    IPC: G11C11/16

    CPC classification number: G11C11/1673 ,  G11C7/065 ,  G11C11/1693 ,  G11C13/004 ,  G11C27/024 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2207/002

    Abstract: A method includes sensing a state of a data cell to generate a data voltage. The state of the data cell corresponds to a state of a programmable resistance based memory element of the data cell. The method further includes sensing a state of a reference cell to generate a reference voltage. The state of the data cell and the state of the reference cell are sensed via a common sensing path. The method further includes determining a logic value of the data cell based on the data voltage and the reference voltage.

    Abstract translation: 一种方法包括感测数据单元的状态以产生数据电压。 数据单元的状态对应于数据单元的基于可编程电阻的存储元件的状态。 该方法还包括感测参考单元的状态以产生参考电压。 通过公共感测路径检测数据信元的状态和参考信元的状态。 该方法还包括基于数据电压和参考电压确定数据单元的逻辑值。

    Dual mode sensing scheme
    20.
    发明授权
    Dual mode sensing scheme 有权

    公开(公告)号：US09666259B1

    公开(公告)日：2017-05-30

    申请号：US15097166

    申请日：2016-04-12

    Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

    Inventor： Seong-Ook Jung ,  Taehui Na ,  Byung Kyu Song ,  Jung Pill Kim ,  Seung Hyuk Kang

    IPC: G11C11/16

    CPC classification number: G11C11/1673 ,  G11C7/062 ,  G11C7/065 ,  G11C11/1675

    Abstract: A method of sensing a data value stored at a memory cell according to a dual mode sensing scheme includes determining, at a sensing circuit, whether a resistance of a magnetic tunnel junction (MTJ) element is within a first range of resistance values, within a second range of resistance values, or within a third range of resistance values. The MTJ element is included in the memory cell. The method also includes determining the data value stored at the memory cell according to a first mode of operation if the resistance of the MTJ element is within the first range of resistance values or within the third range of resistance values. The method further includes determining the data value stored at the memory cell according to a second mode of operation if the resistance of the MTJ element is within the second range of resistance values.

Patent Agency Ranking