公开(公告)号：US20180286800A1

公开(公告)日：2018-10-04

申请号：US15472614

申请日：2017-03-29

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Kambiz Samadi ,  Jing Xie ,  Yang Du

IPC: H01L23/528 ,  H01L27/06 ,  H01L23/522 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/528 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5286 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06544

Abstract: Power distribution networks in a three-dimensional (3D) integrated circuit (IC) (3DIC) are disclosed. In one aspect, a voltage drop within a power distribution network in a 3DIC is reduced to reduce unnecessary power dissipation. In a first aspect, interconnect layers devoted to distribution of power within a given tier of the 3DIC are provided with an increased thickness such that a resistance of such interconnect layers is reduced relative to previously used interconnect layers and also reduced relative to other interconnect layers. Further voltage drop reductions may also be realized by placement of vias used to interconnect different tiers, and particularly, those vias used to interconnect the thickened interconnect layers devoted to the distribution of power. That is, the number, position, and/or arrangement of the vias may be controlled in the 3DIC to reduce the voltage drop.

公开(公告)号：US09098666B2

公开(公告)日：2015-08-04

申请号：US13792486

申请日：2013-03-11

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Shreepad A. Panth ,  Jing Xie ,  Yang Du

IPC: G06F17/50 ,  H01L23/522 ,  G11C5/14 ,  G06F1/32

CPC classification number: G06F17/5072 ,  G06F1/32 ,  G06F1/3287 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/62 ,  G11C5/14 ,  H01L23/5226 ,  H01L2924/0002 ,  H03K19/0008 ,  H01L2924/00

Abstract: Exemplary embodiments of the invention are directed to systems and method for designing a clock distribution network for an integrated circuit. The embodiments identify critical sources of clock skew, tightly control the timing of the clock and build that timing into the overall clock distribution network and integrated circuit design. The disclosed embodiments separate the clock distribution network (CDN), i.e., clock generation circuitry, wiring, buffering and registers, from the rest of the logic to improve the clock tree design and reduce the area footprint. In one embodiment, the CDN is separated to a separate tier of a 3D integrated circuit, and the CDN is connected to the logic tier(s) via high-density inter-tier vias. The embodiments are particularly advantageous for implementation with monolithic 3D integrated circuits.

Abstract translation: 本发明的示例性实施例涉及用于设计用于集成电路的时钟分配网络的系统和方法。 这些实施例确定了时钟偏移的关键来源，紧密地控制时钟的定时并将该时序构建到整个时钟分配网络和集成电路设计中。 所公开的实施例将时钟分配网络（CDN），即时钟生成电路，布线，缓冲和寄存器与逻辑的其余部分分开，以改进时钟树设计并减少面积占用。 在一个实施例中，CDN被分离成3D集成电路的单独层，并且CDN通过高密度层间通孔连接到逻辑层。 这些实施例对于使用单片3D集成电路的实现特别有利。

公开(公告)号：US20140146630A1

公开(公告)日：2014-05-29

申请号：US13792592

申请日：2013-03-11

Applicant: QUALCOMM INCORPORATED

Inventor： Jing Xie ,  Yang Du

IPC: G11C5/14 ,  G06F17/50

CPC classification number: G06F17/5072 ,  G06F1/32 ,  G06F1/3287 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/62 ,  G11C5/14 ,  H01L23/5226 ,  H01L2924/0002 ,  H03K19/0008 ,  H01L2924/00

Abstract: The disclosed embodiments comprise a multi-stage circuit operating across different power domains. The multi-stage circuit may be implemented as a master-slave flip-flop circuit integrated with a level shifter that transfers data across different power domains. The master and slave stages of the flip-flop may be split across two tiers of a 3D IC and may include (i) a level shifter across different power domain integrated within the flip-flop circuit, (ii) reduced one-state writing delays by a self-induced power collapsing technique, (iii) splitting flip-flop power supplies in different tiers using monolithic 3D IC technology, and (iv) cross power domain data transfer between 3D IC tiers.

Abstract translation: 所公开的实施例包括跨越不同功率域操作的多级电路。 多级电路可以实现为与电平转换器集成的主从触发器电路，其在不同的电源域之间传送数据。 触发器的主级和从属级可以分为三层3D IC的两层，并且可以包括（i）跨越触发器电路中的不同功率域的电平移位器，（ii）减少的一状态写入延迟 通过自感电源塌陷技术，（iii）使用单片3D IC技术分割不同层级的触发器电源，以及（iv）3D IC层之间的跨功率域数据传输。

公开(公告)号：US20140145347A1

公开(公告)日：2014-05-29

申请号：US13792486

申请日：2013-03-11

Applicant: QUALCOMM INCORPORATED

Inventor： Kambiz Samadi ,  Shreepad A. Panth ,  Jing Xie ,  Yang Du

IPC: G06F17/50 ,  H01L23/522

CPC classification number: G06F17/5072 ,  G06F1/32 ,  G06F1/3287 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/62 ,  G11C5/14 ,  H01L23/5226 ,  H01L2924/0002 ,  H03K19/0008 ,  H01L2924/00

Abstract: Exemplary embodiments of the invention are directed to systems and method for designing a clock distribution network for an integrated circuit. The embodiments identify critical sources of clock skew, tightly control the timing of the clock and build that timing into the overall clock distribution network and integrated circuit design. The disclosed embodiments separate the clock distribution network (CDN), i.e., clock generation circuitry, wiring, buffering and registers, from the rest of the logic to improve the clock tree design and reduce the area footprint. In one embodiment, the CDN is separated to a separate tier of a 3D integrated circuit, and the CDN is connected to the logic tier(s) via high-density inter-tier vias. The embodiments are particularly advantageous for implementation with monolithic 3D integrated circuits.

Abstract translation: 本发明的示例性实施例涉及用于设计用于集成电路的时钟分配网络的系统和方法。 这些实施例确定了时钟偏移的关键来源，紧密地控制时钟的定时并将该时序构建到整个时钟分配网络和集成电路设计中。 所公开的实施例将时钟分配网络（CDN），即时钟生成电路，布线，缓冲和寄存器与逻辑的其余部分分开，以改进时钟树设计并减少面积占用。 在一个实施例中，CDN被分离成3D集成电路的单独层，并且CDN通过高密度层间通孔连接到逻辑层。 这些实施例对于使用单片3D集成电路的实现特别有利。

公开(公告)号：US09628077B2

公开(公告)日：2017-04-18

申请号：US14638270

申请日：2015-03-04

Applicant: QUALCOMM Incorporated

Inventor： Jing Xie ,  Yang Du

IPC: H03K19/00 ,  H03K3/037 ,  H03K19/0175 ,  H01L25/065 ,  G06F1/32

CPC classification number: H03K19/0021 ,  G06F1/3296 ,  H01L25/0657 ,  H03K3/037 ,  H03K19/017509 ,  Y02D10/172

Abstract: A three-dimensional integrated circuit having a dual or multiple power domain is capable of less energy consumption operation under a given clock rate, which results in an enhanced power-performance-area (PPA) envelope. Sequential logic operates under a system clock that determines the system throughput, whereas combinational logic operates in a different power domain to control overall system power including dynamic and static power. The sequential logic and clock network may be implemented in one tier of the three-dimensional integrated circuit supplied with a relatively high power supply voltage, whereas the combinational logic may be implemented in another tier of the three-dimensional integrated circuit supplied with a relatively low power supply voltage. Further pipeline reorganization may be implemented to leverage the system energy consumption and performance to an optimal point.

公开(公告)号：US09583179B2

公开(公告)日：2017-02-28

申请号：US14790510

申请日：2015-07-02

Applicant: QUALCOMM Incorporated

Inventor： Jing Xie ,  Yang Du

IPC: G11C5/06 ,  G11C11/412 ,  G11C5/02 ,  H01L27/06 ,  H01L27/11 ,  G11C11/419 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522

CPC classification number: G11C11/412 ,  G11C5/025 ,  G11C11/419 ,  H01L21/768 ,  H01L23/481 ,  H01L23/5226 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) (3DIC) tiers is disclosed. Related 3DICs, 3DIC processor cores, and methods are also disclosed. In embodiments disclosed herein, memory read access ports of a memory block are separated from a memory cell in different tiers of a 3DIC. 3DICs achieve higher device packing density, lower interconnect delays, and lower costs. In this manner, different supply voltages can be provided for the read access ports and the memory cell to be able to lower supply voltage for the read access ports. Static noise margins and read/write noise margins in the memory cell may be provided as a result. Providing multiple power supply rails inside a non-separated memory block that increases area can also be avoided.

Abstract translation: 公开了3D集成电路（IC）（3DIC）层中的三维（3D）存储单元分离。 还公开了相关3DIC，3DIC处理器核心和方法。 在本文公开的实施例中，存储器块的存储器读取访问端口与3DIC的不同层级的存储器单元分离。 3DIC实现更高的器件封装密度，更低的互连延迟和更低的成本。 以这种方式，可以为读访问端口和存储单元提供不同的电源电压，以便能够降低读访问端口的电源电压。 结果可能会提供存储单元中的静态噪声容限和读/写噪声余量。 还可以避免增加面积的非分开的存储块内的多个电源轨。

公开(公告)号：US20160285439A1

公开(公告)日：2016-09-29

申请号：US14669030

申请日：2015-03-26

Applicant: QUALCOMM Incorporated

Inventor： Jing Xie ,  Yang Du

IPC: H03K3/3562

CPC classification number: H03K3/35625 ,  H03K3/356139 ,  H03K3/356156 ,  H03K3/356165 ,  H03K3/356191

Abstract: Multi-level conversion flip-flop circuits for multi-power domain integrated circuits (ICs) and related methods are disclosed. A flip-flop circuit latches a representation of a received input data signal in a lower voltage domain, in a latch circuit in a higher voltage domain without need for separate voltage level shifters. As a result, insertion loss/delay is minimized, thereby increasing performance. In certain aspects, the flip-flop circuits employ a gate-controlled, data control transistor to control activation of the latch circuit. By coupling the input data signal to a gate of the data control transistor, the input data signal in the lower voltage domain is not directly latched into the latch circuit. Instead, the data control transistor is configured to activate the latch circuit to latch a voltage in the higher voltage domain representing a logic value of the input data signal in the lower voltage domain in response to a clock signal.

Abstract translation: 公开了用于多功率域集成电路（IC）的多电平转换触发器电路和相关方法。 触发器电路在更高电压域的锁存电路中将接收到的输入数据信号的表示锁存在较低电压域中，而不需要单独的电压电平移位器。 因此，插入损耗/延迟最小化，从而提高性能。 在某些方面，触发器电路采用栅极控制的数据控制晶体管来控制锁存电路的激活。 通过将输入数据信号耦合到数据控制晶体管的栅极，低电压域中的输入数据信号不直接锁存到锁存电路中。 相反，数据控制晶体管被配置为响应于时钟信号而激活锁存电路以锁存代表较低电压域中的输入数据信号的逻辑值的较高电压域中的电压。

公开(公告)号：US20150302919A1

公开(公告)日：2015-10-22

申请号：US14790510

申请日：2015-07-02

Applicant: QUALCOMM Incorporated

Inventor： Jing Xie ,  Yang Du

IPC: G11C11/419 ,  H01L27/06 ,  H01L21/768 ,  H01L23/48 ,  G11C5/02 ,  H01L27/11 ,  H01L23/522

CPC classification number: G11C11/412 ,  G11C5/025 ,  G11C11/419 ,  H01L21/768 ,  H01L23/481 ,  H01L23/5226 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) (3DIC) tiers is disclosed. Related 3DICs, 3DIC processor cores, and methods are also disclosed. In embodiments disclosed herein, memory read access ports of a memory block are separated from a memory cell in different tiers of a 3DIC. 3DICs achieve higher device packing density, lower interconnect delays, and lower costs. In this manner, different supply voltages can be provided for the read access ports and the memory cell to be able to lower supply voltage for the read access ports. Static noise margins and read/write noise margins in the memory cell may be provided as a result. Providing multiple power supply rails inside a non-separated memory block that increases area can also be avoided.

Abstract translation: 公开了3D集成电路（IC）（3DIC）层中的三维（3D）存储单元分离。 还公开了相关3DIC，3DIC处理器核心和方法。 在本文公开的实施例中，存储器块的存储器读取访问端口与3DIC的不同层级的存储器单元分离。 3DIC实现更高的器件封装密度，更低的互连延迟和更低的成本。 以这种方式，可以为读访问端口和存储单元提供不同的电源电压，以便能够降低读访问端口的电源电压。 结果可能会提供存储单元中的静态噪声容限和读/写噪声余量。 还可以避免增加面积的非分开的存储块内的多个电源轨。