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    Adaptive voltage controller
    13.
    发明授权
    Adaptive voltage controller 有权

    公开(公告)号：US11249530B1

    公开(公告)日：2022-02-15

    申请号：US17105253

    申请日：2020-11-25

    Applicant: QUALCOMM Incorporated

    Inventor： Dipti Ranjan Pal ,  Harshat Pant ,  Abinash Roy ,  Shih-Hsin Jason Hu ,  Keith Alan Bowman

    IPC: G06F1/24 ,  G06F1/30 ,  G06F1/324 ,  G05F3/24 ,  G05F1/595

    Abstract: In certain aspects, a system includes a voltage controller, wherein the voltage controller includes switches coupled between a voltage supply rail and an output of the voltage controller, each of the switches having a control input, and a control circuit coupled to the control inputs of the switches. The system also includes a timing circuit coupled to the control circuit, wherein the timing circuit includes a delay line, and flops, each of the flops having an input and an output, wherein the input of each of the flops is coupled to a respective node on the delay line, and the outputs of the flops are coupled to the control circuit.

    POWER DISTRIBUTION NETWORK (PDN) DROOP/OVERSHOOT MITIGATION
    15.
    发明申请
    POWER DISTRIBUTION NETWORK (PDN) DROOP/OVERSHOOT MITIGATION 有权
    电力分配网络（PDN）DROOP / OVERSHOOT MITIGATION

    公开(公告)号：US20170038789A1

    公开(公告)日：2017-02-09

    申请号：US14817057

    申请日：2015-08-03

    Applicant: QUALCOMM Incorporated

    Inventor： Dipti Ranjan Pal ,  Mohamed Waleed Allam ,  Ingyeom Kim ,  Paul Ivan Penzes

    IPC: G06F1/08 ,  G06F1/12

    CPC classification number: G06F1/08 ,  G06F1/12

    Abstract: Systems and methods for power distribution network (PDN) droop/overshoot mitigation are provided. In certain embodiments, overshoot is mitigated by ramping down a frequency of a clock signal to a processor when the processor is switching clock frequencies and/or the processor is transitioning from an active mode to an idle mode. In certain embodiments, droop is mitigated by ramping up a frequency of a clock signal to a processor when the processor is switching clock frequencies and/or the processor is transitioning from an idle mode to an active mode.

    Abstract translation: 提供了配电网络（PDN）下垂/过冲缓解的系统和方法。 在某些实施例中，当处理器切换时钟频率和/或处理器从活动模式转换到空闲模式时，通过将时钟信号的频率降低到处理器来减轻过冲。 在某些实施例中，当处理器切换时钟频率和/或处理器从空闲模式转换到活动模式时，通过将时钟信号的频率上升到处理器来减轻下降。

    REDUCING TEST TIME AND SYSTEM-ON-CHIP (SOC) AREA REDUCTION USING SIMULTANEOUS CLOCK CAPTURE BASED ON VOLTAGE SENSOR INPUT
    16.
    发明申请
    REDUCING TEST TIME AND SYSTEM-ON-CHIP (SOC) AREA REDUCTION USING SIMULTANEOUS CLOCK CAPTURE BASED ON VOLTAGE SENSOR INPUT 审中-公开
    使用基于电压传感器输入的同步时钟捕获减少测试时间和系统片上（SOC）面积减少

    公开(公告)号：US20170010320A1

    公开(公告)日：2017-01-12

    申请号：US14796185

    申请日：2015-07-10

    Applicant: QUALCOMM Incorporated

    Inventor： Dipti Ranjan Pal ,  Kumar Kanti Ghosh

    IPC: G01R31/28

    CPC classification number: G01R31/2834 ,  G01R31/318505 ,  G01R31/318594

    Abstract: A method and apparatus for testing an electronic component is provided. The method begins when a design-for-test (DFT) mode is entered and at least one sensor is enabled. Sensor results are monitored and determine the number of cores or capture domains that may be tested simultaneously. The sensors include a voltage and temperature sensor, and either or both sensors may be enabled during testing. Maximum and minimum voltage levels for each capture domain determine at what value a voltage drop occurs. The number of cores selected minimizes a voltage drop across the electronic component. Maximum and minimum temperatures across the multiple cores of the electronic component determine the number of clocks that may be operated simultaneously during testing. An apparatus includes an electronic device to be tested, test sensors on the electronic device, and an interface to a test fixture.

    Abstract translation: 提供了一种用于测试电子部件的方法和装置。 当输入设计测试（DFT）模式并启用至少一个传感器时，该方法开始。 监测传感器结果，并确定可同时测试的核心或捕获区域的数量。 传感器包括电压和温度传感器，并且在测试期间可以启用任一个或两个传感器。 每个捕获域的最大和最小电压电平都决定了发生电压降的值。 所选择的核心数量使得电子部件上的电压降最小化。 电子元件的多个核心的最大和最小温度决定了在测试期间可同时运行的时钟数。 一种装置包括待测试的电子设备，电子设备上的测试传感器以及与测试夹具的接口。

    DYNAMIC CLOCK AND VOLTAGE SCALING WITH LOW-LATENCY SWITCHING
    17.
    发明申请
    DYNAMIC CLOCK AND VOLTAGE SCALING WITH LOW-LATENCY SWITCHING 有权
    动态时钟和低电平切换低电平切换

    公开(公告)号：US20150227185A1

    公开(公告)日：2015-08-13

    申请号：US14177073

    申请日：2014-02-10

    Applicant: QUALCOMM Incorporated

    Inventor： Dipti Ranjan Pal ,  Paul Ivan Penzes ,  Mohamed Waleed Allam

    IPC: G06F1/32

    CPC classification number: G06F1/3203 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  H03L7/22 ,  Y02D10/126 ,  Y02D10/152

    Abstract: Systems and methods for dynamic clock and voltage scaling can switch integrated circuits between frequency-voltage modes with low latency. These systems include a resource power manager that can control a power management integrated circuit (PMIC), phase locked loops (PLLs), and clock dividers. The resource power manager controls transitions between frequency-voltage modes. The systems and methods provide dynamic clock and voltage scaling where the transitions between frequency-voltage modes are an atomic operation. Additionally, the resource power manager can control many modules, for example, clock dividers, in parallel. The invention can, due to lower latency between frequency-voltage modes, can provide improved system performance and reduced system power.

    Abstract translation: 用于动态时钟和电压缩放的系统和方法可以在低电平时间的频率 - 电压模式之间切换集成电路。 这些系统包括能够控制功率管理集成电路（PMIC），锁相环（PLL）和时钟分频器的资源功率管理器。 资源功率管理器控制频率 - 电压模式之间的转换。 系统和方法提供动态时钟和电压缩放，其中频率 - 电压模式之间的转换是原子操作。 此外，资源功率管理器可以并行地控制许多模块，例如时钟分频器。 由于频率 - 电压模式之间的较低延迟，本发明可以提供改进的系统性能并降低系统功率。

    FRACTIONAL CLOCK GENERATOR WITH RAMP CONTROL INCLUDING FIXED TIME INTERVAL AND COARSE/FINE FREQUENCY CHANGE STEPS
    18.
    发明申请
    FRACTIONAL CLOCK GENERATOR WITH RAMP CONTROL INCLUDING FIXED TIME INTERVAL AND COARSE/FINE FREQUENCY CHANGE STEPS 审中-公开

    公开(公告)号：US20180278261A1

    公开(公告)日：2018-09-27

    申请号：US15987208

    申请日：2018-05-23

    Applicant: QUALCOMM Incorporated

    Inventor： Kevin Bowles ,  Dipti Ranjan Pal

    IPC: H03L7/197 ,  H03K21/10

    CPC classification number: H03L7/1974 ,  H03K3/017 ,  H03K21/10 ,  H03K2005/00013 ,  H03L7/085

    Abstract: A clock signal generator including a fractional clock divider and a frequency ramp control circuit. The fractional clock divider is configured to generate an output clock signal with a frequency being a divider ratio multiplied by a frequency of an input clock signal. The frequency ramp control circuit is configured to provide the fractional clock divider a set of divider ratios so that the frequency of the output clock signal is ramped in steps from a current frequency to a target frequency. The frequency ramp control circuit is configured to produce frequency change steps each having substantially the same duration. The frequency ramp control circuit is also configured to provide the set of divider ratios such as a first portion of the frequency ramp is performed using coarse frequency changes and a second portion of the ramp is performed using at least one fine frequency change.

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