公开(公告)号：US20170038789A1

公开(公告)日：2017-02-09

申请号：US14817057

申请日：2015-08-03

Applicant: QUALCOMM Incorporated

Inventor： Dipti Ranjan Pal ,  Mohamed Waleed Allam ,  Ingyeom Kim ,  Paul Ivan Penzes

IPC: G06F1/08 ,  G06F1/12

CPC classification number: G06F1/08 ,  G06F1/12

Abstract: Systems and methods for power distribution network (PDN) droop/overshoot mitigation are provided. In certain embodiments, overshoot is mitigated by ramping down a frequency of a clock signal to a processor when the processor is switching clock frequencies and/or the processor is transitioning from an active mode to an idle mode. In certain embodiments, droop is mitigated by ramping up a frequency of a clock signal to a processor when the processor is switching clock frequencies and/or the processor is transitioning from an idle mode to an active mode.

Abstract translation: 提供了配电网络（PDN）下垂/过冲缓解的系统和方法。 在某些实施例中，当处理器切换时钟频率和/或处理器从活动模式转换到空闲模式时，通过将时钟信号的频率降低到处理器来减轻过冲。 在某些实施例中，当处理器切换时钟频率和/或处理器从空闲模式转换到活动模式时，通过将时钟信号的频率上升到处理器来减轻下降。

公开(公告)号：US09778676B2

公开(公告)日：2017-10-03

申请号：US14817057

申请日：2015-08-03

Applicant: QUALCOMM Incorporated

Inventor： Dipti Ranjan Pal ,  Mohamed Waleed Allam ,  Ingyeom Kim ,  Paul Ivan Penzes

IPC: G06F1/00 ,  G06F1/08 ,  G06F1/12

CPC classification number: G06F1/08 ,  G06F1/12

Abstract: Systems and methods for power distribution network (PDN) droop/overshoot mitigation are provided. In certain embodiments, overshoot is mitigated by ramping down a frequency of a clock signal to a processor when the processor is switching clock frequencies and/or the processor is transitioning from an active mode to an idle mode. In certain embodiments, droop is mitigated by ramping up a frequency of a clock signal to a processor when the processor is switching clock frequencies and/or the processor is transitioning from an idle mode to an active mode.