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    Processor security mode based memory operation management
    3.
    发明授权
    Processor security mode based memory operation management 有权

    公开(公告)号：US11604505B2

    公开(公告)日：2023-03-14

    申请号：US17136175

    申请日：2020-12-29

    Applicant: QUALCOMM incorporated

    Inventor： Bharat Kumar Rangarajan ,  Rajesh Arimilli ,  Rengarajan Ragavan

    IPC: G06F1/3237 ,  G06F21/74 ,  G06F3/06 ,  G06F15/78

    Abstract: Various embodiments include methods and devices for system on chip infrastructure of system on chip infrastructure secure memory access and power management. Some embodiments, include determining whether a processor is performing a secure memory access transaction, and gating a clock signal from being transmitted to a secure portion of a memory in response to determining that the processor is not performing a secure memory access transaction. Some embodiments include determining whether any processor is operating in a secure mode, and transmitting a retention signal to the secure portion of the memory in response to determining that no processor is operating in a secure mode. The retention signal may be configured to set a retention state for the secure portion of the memory.

    Asymmetric memory tag access and design
    5.
    发明授权
    Asymmetric memory tag access and design 有权

    公开(公告)号：US10831667B2

    公开(公告)日：2020-11-10

    申请号：US16173221

    申请日：2018-10-29

    Applicant: QUALCOMM Incorporated

    Inventor： Bharat Kumar Rangarajan ,  Chulmin Jung ,  Rakesh Misra

    IPC: G06F12/0846 ,  G06F12/0808 ,  G06F12/0891 ,  G06F12/0895

    Abstract: Various aspects are described herein. In some aspects, the disclosure provides techniques for accessing tag information in a memory line. The techniques include determining an operation to perform on at least one memory line of a memory. The techniques further include performing the operation by accessing only a portion of the at least one memory line, wherein the only the portion of the at least one memory line comprises one or more flag bits that are independently accessible from remaining bits of the at least one memory line.

    Selective coupling of memory to voltage rails based on operating mode of processor
    6.
    发明授权
    Selective coupling of memory to voltage rails based on operating mode of processor 有权

    公开(公告)号：US10691195B2

    公开(公告)日：2020-06-23

    申请号：US15908534

    申请日：2018-02-28

    Applicant: QUALCOMM Incorporated

    Inventor： Raghavendra Srinivas ,  Bharat Kumar Rangarajan ,  Rajesh Arimilli

    IPC: G06F1/00 ,  G06F1/3296 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/324 ,  G11C5/14 ,  G06F1/3206 ,  G06F1/26

    Abstract: Various aspects are described herein. In some aspects, the disclosure provides selective coupling of portions of a memory structure to voltage supplies. Certain aspects provide a computing device. The computing device includes a memory comprising a plurality of portions that are individually power collapsible. The computing device further includes a first voltage rail supplying a first voltage. The computing device further includes a second voltage rail supplying a second voltage. The computing device further includes a plurality of switching circuits, each switching circuit configured to selectively couple a corresponding one of the plurality of portions with the first voltage rail or the second voltage rail. The computing device further includes a controller configured to control each of the plurality of switching circuits based on a current active mode of the memory, and a current operating mode of each of the plurality of portions.

    METHOD AND SYSTEM FOR WAKING UP A CPU FROM A POWER-SAVING MODE
    8.
    发明申请
    METHOD AND SYSTEM FOR WAKING UP A CPU FROM A POWER-SAVING MODE 有权

    公开(公告)号：US20210157382A1

    公开(公告)日：2021-05-27

    申请号：US16697293

    申请日：2019-11-27

    Applicant: QUALCOMM INCORPORATED

    Inventor： Bharat Kumar Rangarajan ,  Rajesh Arimilli

    IPC: G06F1/3206

    Abstract: A CPU core may be woken up from a power-saving mode in a portable computing device in a manner that depends upon whether the wake-up event source is a snoop request or an interrupt. A core power controller may monitor for and detect snoop requests and interrupts directed to the CPU core while the CPU core is in the power-saving mode. In response to detecting a snoop request, the core power controller may wake up snoop-related components of the CPU core while refraining from waking up non-snoop-related components of the CPU core. In response to detecting an interrupt, the core power controller may wake up both the snoop-related components and the non-snoop-related components of the CPU core.

    Memory leakage power savings
    9.
    发明授权
    Memory leakage power savings 有权

    公开(公告)号：US10248558B2

    公开(公告)日：2019-04-02

    申请号：US15690197

    申请日：2017-08-29

    Applicant: QUALCOMM Incorporated

    Inventor： Bharat Kumar Rangarajan ,  Rakesh Misra

    IPC: G06F3/06 ,  G06F12/08 ,  G06F1/32 ,  G06F12/02 ,  G06F1/3206 ,  G06F1/3234 ,  G06F11/36 ,  H02H3/32

    Abstract: In some aspects, a method for managing leakage power includes coupling a first supply rail to a cache memory if a processor is in a first performance mode, wherein the processor accesses the cache memory, and coupling a second supply rail to the cache memory if the processor is in a second performance mode. The method also includes detecting gating of a clock signal to the cache memory or the processor, and, upon detecting gating of the clock signal, switching the cache memory from the second supply rail to the first supply rail if the cache memory is currently coupled to the second supply rail.

    MEMORY LEAKAGE POWER SAVINGS
    10.
    发明申请
    MEMORY LEAKAGE POWER SAVINGS 审中-公开

    公开(公告)号：US20190065359A1

    公开(公告)日：2019-02-28

    申请号：US15690197

    申请日：2017-08-29

    Applicant: QUALCOMM Incorporated

    Inventor： Bharat Kumar Rangarajan ,  Rakesh Misra

    IPC: G06F12/02 ,  G06F1/32 ,  G06F11/36 ,  H02H3/32

    Abstract: In some aspects, a method for managing leakage power includes coupling a first supply rail to a cache memory if a processor is in a first performance mode, wherein the processor accesses the cache memory, and coupling a second supply rail to the cache memory if the processor is in a second performance mode. The method also includes detecting gating of a clock signal to the cache memory or the processor, and, upon detecting gating of the clock signal, switching the cache memory from the second supply rail to the first supply rail if the cache memory is currently coupled to the second supply rail.

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