公开(公告)号：US09529666B2

公开(公告)日：2016-12-27

申请号：US14295355

申请日：2014-06-04

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Shao-Wei Yen ,  Yu-Hsiang Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai ,  Siu-Tung Lam

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/42 ,  H03M13/37 ,  H03M13/00 ,  H03M13/11 ,  H03M13/15 ,  H03M13/23

CPC classification number: G06F11/1008 ,  G06F11/1012 ,  G11C29/42 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/152 ,  H03M13/23 ,  H03M13/3715 ,  H03M13/3723 ,  H03M13/6325

Abstract: A decoding method, a memory storage device and a memory controlling circuit are provided. The decoding method includes: sending a read command sequence configured to read the memory cells, so as to obtain a plurality of first verification bits; executing a first decoding procedure according to the first verification bits, and determining whether a first valid codeword is generated; if the first valid codeword is not generated, sending another read command sequence configured to obtain a plurality of second verification bits; calculating a total number of the memory cells conforming to a specific condition according to the second verification bits; obtaining a channel reliability message according to the total number; and executing a second decoding procedure according to the channel reliability message. Accordingly, a correcting ability of decoding may be improved.

Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路。 解码方法包括：发送配置为读取存储单元的读命令序列，以获得多个第一验证位; 执行根据所述第一验证比特的第一解码过程，以及确定是否生成第一有效码字; 如果不产生第一有效码字，则发送另一读取命令序列，被配置为获得多个第二验证比特; 根据第二验证位计算符合特定条件的存储单元的总数; 根据总数获取信道可靠性消息; 以及根据信道可靠性消息执行第二解码过程。 因此，可以提高解码的校正能力。

公开(公告)号：US20150095741A1

公开(公告)日：2015-04-02

申请号：US14109959

申请日：2013-12-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Shao-Wei Yen ,  Yu-Hsiang Lin ,  Kuo-Hsin Lai ,  Kuo-Yi Cheng

IPC: G06F11/10

CPC classification number: G06F11/1008 ,  G06F11/1048

Abstract: A decoding method, a memory storage device and a memory controlling circuit unit are provided. The method includes: reading memory cells according to a first reading voltage to obtain first verifying bits; executing a decoding procedure including a probability decoding algorithm according to the first verifying bits to obtain first decoded bits, and determining whether a decoding is successful by using the decoded bits; if the decoding is failed, reading the memory cells according to a second reading voltage to obtain second verifying bits, and executing the decoding procedure according to the second verifying bits to obtain second decoded bits. The second reading voltage is different from the first reading voltage, and the number of the second reading voltage is equal to the number of the first reading voltage. Accordingly, the ability for correcting errors is improved.

Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路单元。 该方法包括：根据第一读取电压读取存储器单元以获得第一验证位; 执行包括根据第一验证位的概率解码算法的解码过程以获得第一解码比特，并且通过使用解码比特来确定解码是否成功; 如果解码失败，则根据第二读取电压读取存储器单元以获得第二验证位，并且根据第二验证位执行解码过程以获得第二解码位。 第二读取电压与第一读取电压不同，第二读取电压的数量等于第一读取电压的数量。 因此，能够提高校正误差的能力。

公开(公告)号：US11190217B2

公开(公告)日：2021-11-30

申请号：US16788320

申请日：2020-02-12

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Hsiang Lin ,  Shao-Wei Yen ,  Chih-Kang Yeh

IPC: H03M13/29 ,  G06F11/10 ,  H03M13/53

Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: obtaining a data; encoding a plurality of sub-data in the data to obtain a plurality of first error checking and correction codes respectively corresponding to the plurality of sub-data; writing the plurality of sub-data and the plurality of first error checking and correction codes into a first physical programming unit; encoding the plurality of sub-data to obtain a second error checking and correction code; and writing the second error checking and correction code into a second physical programming unit.

公开(公告)号：US20190114227A1

公开(公告)日：2019-04-18

申请号：US15831405

申请日：2017-12-05

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Hsiang Lin ,  Shao-Wei Yen ,  Yu-Siang Yang ,  Kuo-Hsin Lai

IPC: G06F11/10 ,  G11C29/52

Abstract: A decoding method is provided according to an exemplary embodiment of the invention. The decoding method includes: reading a data set from at least two physical units of a rewritable non-volatile memory module by using at least one read voltage level; performing a first-type decoding operation for first data by using the data set and recording decoding information of the first-type decoding operation if the data set conforms to a default condition; adjusting reliability information corresponding to the first data according to the recorded decoding information, and the reliability information is not used in the first-type decoding operation, and the adjusted reliability information is different from default reliability information corresponding to the first data; and performing a second-type decoding operation for the first data according to the adjusted reliability information.

公开(公告)号：US20160098316A1

公开(公告)日：2016-04-07

申请号：US14565437

申请日：2014-12-10

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Shao-Wei Yen ,  Tien-Ching Wang ,  Yu-Hsiang Lin ,  Kuo-Hsin Lai ,  Li-Chun Liang

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C11/5642 ,  G11C16/349 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0409

Abstract: An error processing method for a rewritable non-volatile memory module, a memory storage device and a memory controlling circuit unit are provided. The rewritable non-volatile memory module includes a plurality of memory cells. The error processing method includes: sending a first read command sequence for reading a plurality of bits from the memory cells; performing a first decoding on the bits; determining whether each error belongs to a first type error or a second type error if the bits have at least one error; recording related information of a first error in the at least one error if the first error belongs to the first type error; and not recording the related information of the first error if the first error belongs to the second type error. Accordingly, errors with particular type may be processed suitably.

Abstract translation: 提供了一种用于可重写非易失性存储器模块，存储器存储装置和存储器控制电路单元的错误处理方法。 可重写非易失性存储器模块包括多个存储单元。 该错误处理方法包括：从存储器单元发送用于读取多个位的第一读取命令序列; 对比特执行第一解码; 如果所述比特具有至少一个错误，则确定每个错误是否属于第一类型错误或第二类型错误; 如果所述第一错误属于所述第一类型错误，则记录所述至少一个错误中的第一错误的相关信息; 并且如果第一错误属于第二类型错误，则不记录第一错误的相关信息。 因此，可以适当地处理特定类型的错误。

公开(公告)号：US20150293813A1

公开(公告)日：2015-10-15

申请号：US14296383

申请日：2014-06-04

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Shao-Wei Yen ,  Yu-Hsiang Lin ,  Kuo-Hsin Lai

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/37

CPC classification number: G11C29/52 ,  G06F11/1012 ,  G11C2029/0411 ,  H03M13/05 ,  H03M13/3746

Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided, the decoding method includes: reading a plurality of memory cells according to hard decision voltage to obtain hard bit; performing a parity check procedure for the hard bit to obtain a plurality of syndromes; determining whether the hard bit has error according to the syndromes; if the hard bit has the error, updating the hard bit according to channel information of the hard bit and syndrome weight information corresponding to the hard bit.

Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路单元，该解码方法包括：根据硬判定电压读取多个存储单元以获得硬比特; 对所述硬比特执行奇偶校验处理以获得多个综合征; 根据综合征确定硬比特是否有错误; 如果硬比特错误，则根据与硬比特相对应的硬比特和综合征权重信息的信道信息更新硬比特。

公开(公告)号：US20150293811A1

公开(公告)日：2015-10-15

申请号：US14295355

申请日：2014-06-04

Applicant: Phison Electronics Corp.

Inventor： Wei Lin ,  Shao-Wei Yen ,  Yu-Hsiang Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai ,  Siu-Tung Lam

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/11

CPC classification number: G06F11/1008 ,  G06F11/1012 ,  G11C29/42 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/152 ,  H03M13/23 ,  H03M13/3715 ,  H03M13/3723 ,  H03M13/6325

Abstract: A decoding method, a memory storage device and a memory controlling circuit are provided. The decoding method includes: sending a read command sequence configured to read the memory cells, so as to obtain a plurality of first verification bits; executing a first decoding procedure according to the first verification bits, and determining whether a first valid codeword is generated; if the first valid codeword is not generated, sending another read command sequence configured to obtain a plurality of second verification bits; calculating a total number of the memory cells conforming to a specific condition according to the second verification bits; obtaining a channel reliability message according to the total number; and executing a second decoding procedure according to the channel reliability message. Accordingly, a correcting ability of decoding may be improved.

Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路。 解码方法包括：发送配置为读取存储单元的读命令序列，以获得多个第一验证位; 执行根据所述第一验证比特的第一解码过程，以及确定是否生成第一有效码字; 如果不产生第一有效码字，则发送另一读取命令序列，被配置为获得多个第二验证比特; 根据第二验证位计算符合特定条件的存储单元的总数; 根据总数获取信道可靠性消息; 以及根据信道可靠性消息执行第二解码过程。 因此，可以提高解码的校正能力。

公开(公告)号：US09136875B2

公开(公告)日：2015-09-15

申请号：US14054848

申请日：2013-10-16

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shao-Wei Yen ,  Yu-Hsiang Lin ,  Wei Lin ,  Kuo-Hsin Lai ,  Kuo-Yi Cheng

IPC: G06F11/10 ,  H03M13/11

CPC classification number: H03M13/1105 ,  G06F11/10 ,  G06F11/1048 ,  H03M13/1111 ,  H03M13/3723 ,  H03M13/6577

Abstract: A decoding method, a memory storage device and a rewritable non-volatile memory module are provided. The method includes: reading a plurality of bits from the rewritable non-volatile memory module according to a reading voltage; performing a parity check of a low density parity check (LDPC) algorithm on the bits to obtain syndromes, and each of the bits is corresponding to at least one of the syndromes; determining whether the bits have an error according to the syndromes; if the bits have the error, obtaining a syndrome weight of each of the bits according to the syndromes corresponding to each of the bits; obtaining an initial value of each of the bits according to the syndrome weight of each of the bits; and performing a first iteration decoding of the LDPC algorithm on the bits according to the initial values. Accordingly, the decoding speed is increased.

Abstract translation: 提供了解码方法，存储器存储装置和可重写非易失性存储器模块。 该方法包括：根据读取电压从可重写非易失性存储器模块读取多个位; 对比特执行低密度奇偶校验（LDPC）算法的奇偶校验以获得校正子，并且每个比特对应于至少一个综合征; 确定所述位是否具有根据所述综合征的错误; 如果这些比特具有错误，则根据与每个比特对应的校验子获得每个比特的综合征权重; 根据每个位的校正子权重获得每个比特的初始值; 以及根据初始值对该比特执行LDPC算法的第一迭代解码。 因此，解码速度增加。

公开(公告)号：US20150067446A1

公开(公告)日：2015-03-05

申请号：US14054848

申请日：2013-10-16

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shao-Wei Yen ,  Yu-Hsiang Lin ,  Wei Lin ,  Kuo-Hsin Lai ,  Kuo-Yi Cheng

IPC: H03M13/11 ,  G06F11/10

CPC classification number: H03M13/1105 ,  G06F11/10 ,  G06F11/1048 ,  H03M13/1111 ,  H03M13/3723 ,  H03M13/6577

Abstract: A decoding method, a memory storage device and a rewritable non-volatile memory module are provided. The method includes: reading a plurality of bits from the rewritable non-volatile memory module according to a reading voltage; performing a parity check of a low density parity check (LDPC) algorithm on the bits to obtain syndromes, and each of the bits is corresponding to at least one of the syndromes; determining whether the bits have an error according to the syndromes; if the bits have the error, obtaining a syndrome weight of each of the bits according to the syndromes corresponding to each of the bits; obtaining an initial value of each of the bits according to the syndrome weight of each of the bits; and performing a first iteration decoding of the LDPC algorithm on the bits according to the initial values. Accordingly, the decoding speed is increased.

Abstract translation: 提供了解码方法，存储器存储装置和可重写非易失性存储器模块。 该方法包括：根据读取电压从可重写非易失性存储器模块读取多个位; 对比特执行低密度奇偶校验（LDPC）算法的奇偶校验以获得校正子，并且每个比特对应于至少一个综合征; 确定所述位是否具有根据所述综合征的错误; 如果这些比特具有错误，则根据与每个比特对应的校验子获得每个比特的综合征权重; 根据每个位的校正子权重获得每个比特的初始值; 以及根据初始值对该比特执行LDPC算法的第一迭代解码。 因此，解码速度增加。

公开(公告)号：US20200186171A1

公开(公告)日：2020-06-11

申请号：US16788320

申请日：2020-02-12

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Hsiang Lin ,  Shao-Wei Yen ,  Chih-Kang Yeh

IPC: H03M13/29 ,  G06F11/10

Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: obtaining a data; encoding a plurality of sub-data in the data to obtain a plurality of first error checking and correction codes respectively corresponding to the plurality of sub-data; writing the plurality of sub-data and the plurality of first error checking and correction codes into a first physical programming unit; encoding the plurality of sub-data to obtain a second error checking and correction code; and writing the second error checking and correction code into a second physical programming unit.