公开(公告)号：US08278173B2

公开(公告)日：2012-10-02

申请号：US12827512

申请日：2010-06-30

Applicant: Peng-Soon Lim ,  Chia-Pin Lin ,  Kuang-Yuan Hsu

Inventor： Peng-Soon Lim ,  Chia-Pin Lin ,  Kuang-Yuan Hsu

IPC: H01L21/8234

CPC classification number: H01L27/092 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: A method includes: forming first and second projections; forming a first structure engaging the first projection, and including: a non-metallic conductive layer, and a first opening over the conductive layer; forming a second structure engaging the second projection, and including: a second opening; and conformally depositing a pure metal in the first and second openings. A different aspect involves an apparatus including: a first device that includes a first projection and a first gate structure, the first projection extending from a substrate, and the first gate structure engaging the first projection, and including an opening, and a conformal, pure metal disposed in the opening; and a second device that includes a second projection and a second gate structure, the second projection extending from the substrate, and the second gate structure engaging the second projection, and including a silicide including a metal that is the same metal disposed in the opening.

Abstract translation: 一种方法包括：形成第一和第二突起; 形成与所述第一突起接合的第一结构，并且包括：非金属导电层和所述导电层上的第一开口; 形成与第二突起接合的第二结构，并且包括：第二开口; 并且在第一和第二开口中共形沉积纯金属。 不同的方面涉及一种装置，包括：第一装置，其包括第一突起和第一栅极结构，第一突起从基板延伸，第一栅极结构与第一突起接合，并且包括开口和保形的纯的 设置在开口中的金属; 以及第二装置，其包括第二突起和第二栅极结构，所述第二突起从所述基板延伸，所述第二栅极结构接合所述第二突起，并且包括包含设置在所述开口中的相同金属的金属的硅化物。

公开(公告)号：US20120001266A1

公开(公告)日：2012-01-05

申请号：US12827512

申请日：2010-06-30

Applicant: Peng-Soon Lim ,  Chia-Pin Lin ,  Kuang- Yuan Hsu

Inventor： Peng-Soon Lim ,  Chia-Pin Lin ,  Kuang- Yuan Hsu

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: A method includes: forming first and second projections; forming a first structure engaging the first projection, and including: a non-metallic conductive layer, and a first opening over the conductive layer; forming a second structure engaging the second projection, and including: a second opening; and conformally depositing a pure metal in the first and second openings. A different aspect involves an apparatus including: a first device that includes a first projection and a first gate structure, the first projection extending from a substrate, and the first gate structure engaging the first projection, and including an opening, and a conformal, pure metal disposed in the opening; and a second device that includes a second projection and a second gate structure, the second projection extending from the substrate, and the second gate structure engaging the second projection, and including a silicide including a metal that is the same metal disposed in the opening.

Abstract translation: 一种方法包括：形成第一和第二突起; 形成与所述第一突起接合的第一结构，并且包括：非金属导电层和所述导电层上的第一开口; 形成与第二突起接合的第二结构，并且包括：第二开口; 并在第一和第二开口中共形沉积纯金属。 不同的方面涉及一种装置，包括：第一装置，其包括第一突起和第一栅极结构，第一突起从基板延伸，第一栅极结构与第一突起接合，并且包括开口和保形的纯的 设置在开口中的金属; 以及第二装置，其包括第二突起和第二栅极结构，所述第二突起从所述基板延伸，所述第二栅极结构接合所述第二突起，并且包括包含设置在所述开口中的相同金属的金属的硅化物。

公开(公告)号：US08258587B2

公开(公告)日：2012-09-04

申请号：US12561358

申请日：2009-09-17

Applicant: Yuri Masuoka ,  Shyh-Horng Yang ,  Peng-Soon Lim

Inventor： Yuri Masuoka ,  Shyh-Horng Yang ,  Peng-Soon Lim

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L21/28114 ,  H01L21/28088 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/7833

Abstract: The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a metal gate layer on the high k dielectric material layer; forming a top gate layer on the metal gate layer; patterning the top gate layer, the metal gate layer and the high k dielectric material layer to form a gate stack; performing an etching process to selectively recess the metal gate layer; and forming a gate spacer on sidewalls of the gate stack.

Abstract translation: 本公开提供了制造具有金属栅极叠层的半导体器件的方法。 该方法包括在半导体衬底上形成高k电介质材料层; 在高k电介质材料层上形成金属栅极层; 在所述金属栅极层上形成顶栅层; 图案化顶栅层，金属栅极层和高k电介质材料层以形成栅叠层; 执行蚀刻工艺以选择性地凹陷金属栅极层; 以及在所述栅极堆叠的侧壁上形成栅极间隔物。

公开(公告)号：US20100081262A1

公开(公告)日：2010-04-01

申请号：US12411546

申请日：2009-03-26

Applicant: Peng-Soon Lim ,  Yong-Tian Hou ,  Chien-Hao Chen ,  Chi-Chun Chen

Inventor： Peng-Soon Lim ,  Yong-Tian Hou ,  Chien-Hao Chen ,  Chi-Chun Chen

IPC: H01L21/3205 ,  H01L21/20 ,  H01L21/31

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66636

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a substrate having a first region and a second region, forming first and second gate stacks in the first and second regions, respectively, the first gate stack including a first dummy gate and the second gate stack including a second dummy gate, removing the first dummy gate in the first gate stack thereby forming a first trench and removing the second dummy gate in the second gate stack thereby forming a second trench, forming a first metal layer in the first trench and in the second trench, removing at least a portion of the first metal layer in the first trench, forming a second metal layer in the remainder of the first trench and in the remainder of the second trench, reflowing the second metal layer, and performing a chemical mechanical polishing (CMP).

Abstract translation: 本公开提供一种制造半导体器件的方法，其包括提供具有第一区域和第二区域的衬底，分别在第一和第二区域中形成第一和第二栅极堆叠，第一栅极堆叠包括第一虚拟栅极和 所述第二栅极堆叠包括第二伪栅极，去除所述第一栅极堆叠中的所述第一伪栅极，从而形成第一沟槽并且去除所述第二栅极堆叠中的所述第二伪栅极，从而形成第二沟槽，从而形成第一栅极堆叠中的第一金属层 沟槽，并且在第二沟槽中，去除第一沟槽中的第一金属层的至少一部分，在第一沟槽的其余部分和第二沟槽的其余部分中形成第二金属层，回流第二金属层，以及 进行化学机械抛光（CMP）。

公开(公告)号：US20080096336A1

公开(公告)日：2008-04-24

申请号：US11583500

申请日：2006-10-18

Applicant: Peng-Soon Lim ,  Yong-Tian Hou ,  Jin Ying ,  Hun-Jan Tao

Inventor： Peng-Soon Lim ,  Yong-Tian Hou ,  Jin Ying ,  Hun-Jan Tao

IPC: H01L21/337

CPC classification number: H01L21/823814 ,  H01L21/28097 ,  H01L21/823807 ,  H01L29/66636 ,  H01L29/7848

Abstract: An n-FET and a p-FET each have elevated source/drain structures. Optionally, the p-FET elevated-SOURCE/DRAIN structure is epitaxially grown from a p-FET recess formed in the substrate. Optionally, the n-FET elevated-SOURCE/DRAIN structure is epitaxially grown from an n-FET recess formed in the substrate. The n-FET and p-FET elevated-source/drain structures are both silicided, even though the structures may have different materials and/or different structure heights. At least a thermal treatment portion of the source/drain structure siliciding is performed simultaneously for the n-FET and p-FET elevated source/drain structures. Also, the p-FET gate electrode, the n-FET gate electrode, or both, may optionally be silicided simultaneously (same metal and/or same thermal treatment step) with the n-FET and p-FET elevated-source/drain structures, respectively; even though the gate electrodes may have different materials, different silicide metal, and/or different electrode heights. The silicides formed on n-FET and p-FET elevated-source/drain structures preferably do not extend below a top surface of the substrate more than about 250 angstroms; and the structure heights may be selected to provide this.

Abstract translation: n-FET和p-FET各自具有升高的源极/漏极结构。 可选地，p-FET升高的SOURCE / DRAIN结构从形成在衬底中的p-FET凹槽外延生长。 可选地，n-FET升高的SOURCE / DRAIN结构从形成在衬底中的n-FET凹槽外延生长。 即使结构可能具有不同的材料和/或不同的结构高度，n-FET和p-FET升高源极/漏极结构都是硅化的。 对于n-FET和p-FET升高的源极/漏极结构，至少对源极/漏极结构硅化物的热处理部分同时进行。 此外，p-FET栅电极，n-FET栅电极或两者可以可选地与n-FET和p-FET升高源极/漏极结构同时（相同的金属和/或相同的热处理步骤）硅化 ， 分别; 即使栅电极可以具有不同的材料，不同的硅化物金属和/或不同的电极高度。 在n-FET和p-FET升高源极/漏极结构上形成的硅化物优选不超过约250埃延伸到衬底的顶表面下方; 并且可以选择结构高度来提供这一点。

公开(公告)号：US08114721B2

公开(公告)日：2012-02-14

申请号：US12638958

申请日：2009-12-15

Applicant: Shun Wu Lin ,  Peng-Soon Lim ,  Matt Yeh ,  Ouyang Hui

Inventor： Shun Wu Lin ,  Peng-Soon Lim ,  Matt Yeh ,  Ouyang Hui

IPC: H01L21/84 ,  H01L21/00

CPC classification number: H01L29/66795 ,  H01L29/785

Abstract: A method of forming a FinFET device is provided. In one embodiment, a fin is formed on a substrate. A gate structure is formed over the fin, the gate structure having a dielectric layer and a conformal first polysilicon layer formed above the dielectric layer. An etch stop layer is formed above the first polysilicon layer and thereafter a second polysilicon layer is formed above the etch stop layer. The second polysilicon layer and the etch stop layer are removed. A metal layer is formed above the first polysilicon layer. The first polysilicon layer is reacted with the metal layer to silicide the first polysilicon layer. Any un-reacted metal layer is thereafter removed and source and drain regions are formed on opposite sides of the fin.

Abstract translation: 提供了一种形成FinFET器件的方法。 在一个实施例中，在衬底上形成翅片。 栅极结构形成在鳍片上，栅极结构具有介电层和形成在电介质层上方的共形第一多晶硅层。 在第一多晶硅层上方形成蚀刻停止层，此后在蚀刻停止层上方形成第二多晶硅层。 去除第二多晶硅层和蚀刻停止层。 金属层形成在第一多晶硅层的上方。 第一多晶硅层与金属层反应以使第一多晶硅层硅化。 此后除去任何未反应的金属层，并且在鳍的相对侧上形成源区和漏区。

公开(公告)号：US07465634B2

公开(公告)日：2008-12-16

申请号：US11583500

申请日：2006-10-18

Applicant: Peng-Soon Lim ,  Yong-Tian Hou ,  Jin Ying ,  Hun-Jan Tao

Inventor： Peng-Soon Lim ,  Yong-Tian Hou ,  Jin Ying ,  Hun-Jan Tao

IPC: H01L21/336

CPC classification number: H01L21/823814 ,  H01L21/28097 ,  H01L21/823807 ,  H01L29/66636 ,  H01L29/7848

Abstract: An n-FET and a p-FET each have elevated source/drain structures. Optionally, the p-FET elevated-SOURCE/DRAIN structure is epitaxially grown from a p-FET recess formed in the substrate. Optionally, the n-FET elevated-SOURCE/DRAIN structure is epitaxially grown from an n-FET recess formed in the substrate. The n-FET and p-FET elevated-source/drain structures are both silicided, even though the structures may have different materials and/or different structure heights. At least a thermal treatment portion of the source/drain structure siliciding is performed simultaneously for the n-FET and p-FET elevated source/drain structures. Also, the p-FET gate electrode, the n-FET gate electrode, or both, may optionally be silicided simultaneously (same metal and/or same thermal treatment step) with the n-FET and p-FET elevated-source/drain structures, respectively; even though the gate electrodes may have different materials, different silicide metal, and/or different electrode heights. The silicides formed on n-FET and p-FET elevated-source/drain structures preferably do not extend below a top surface of the substrate more than about 250 angstroms; and the structure heights may be selected to provide this.

公开(公告)号：US20110143510A1

公开(公告)日：2011-06-16

申请号：US12638958

申请日：2009-12-15

Applicant: Shun Wu LIN ,  Peng-Soon Lim ,  Matt Yeh ,  Ouyang Hui

Inventor： Shun Wu LIN ,  Peng-Soon Lim ,  Matt Yeh ,  Ouyang Hui

IPC: H01L21/336

CPC classification number: H01L29/66795 ,  H01L29/785

Abstract: A method of forming a FinFET device is provided. In one embodiment, a fin is formed on a substrate. A gate structure is formed over the fin, the gate structure having a dielectric layer and a conformal first polysilicon layer formed above the dielectric layer. An etch stop layer is formed above the first polysilicon layer and thereafter a second polysilicon layer is formed above the etch stop layer. The second polysilicon layer and the etch stop layer are removed. A metal layer is formed above the first polysilicon layer. The first polysilicon layer is reacted with the metal layer to silicide the first polysilicon layer. Any un-reacted metal layer is thereafter removed and source and drain regions are formed on opposite sides of the fin.

Abstract translation: 提供了一种形成FinFET器件的方法。 在一个实施例中，在衬底上形成翅片。 栅极结构形成在鳍片上，栅极结构具有介电层和形成在电介质层上方的共形第一多晶硅层。 在第一多晶硅层上方形成蚀刻停止层，此后在蚀刻停止层上方形成第二多晶硅层。 去除第二多晶硅层和蚀刻停止层。 金属层形成在第一多晶硅层的上方。 第一多晶硅层与金属层反应以使第一多晶硅层硅化。 此后除去任何未反应的金属层，并且在鳍的相对侧上形成源区和漏区。

公开(公告)号：US07871915B2

公开(公告)日：2011-01-18

申请号：US12411546

申请日：2009-03-26

Applicant: Peng-Soon Lim ,  Yong-Tian Hou ,  Chien-Hao Chen ,  Chi-Chun Chen

Inventor： Peng-Soon Lim ,  Yong-Tian Hou ,  Chien-Hao Chen ,  Chi-Chun Chen

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66636

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a substrate having a first region and a second region, forming first and second gate stacks in the first and second regions, respectively, the first gate stack including a first dummy gate and the second gate stack including a second dummy gate, removing the first dummy gate in the first gate stack thereby forming a first trench and removing the second dummy gate in the second gate stack thereby forming a second trench, forming a first metal layer in the first trench and in the second trench, removing at least a portion of the first metal layer in the first trench, forming a second metal layer in the remainder of the first trench and in the remainder of the second trench, reflowing the second metal layer, and performing a chemical mechanical polishing (CMP).

Abstract translation: 本公开提供一种制造半导体器件的方法，其包括提供具有第一区域和第二区域的衬底，分别在第一和第二区域中形成第一和第二栅极堆叠，第一栅极堆叠包括第一虚拟栅极和 所述第二栅极堆叠包括第二伪栅极，去除所述第一栅极堆叠中的所述第一伪栅极，从而形成第一沟槽并且去除所述第二栅极堆叠中的所述第二伪栅极，从而形成第二沟槽，从而形成第一栅极堆叠中的第一金属层 沟槽，并且在第二沟槽中，去除第一沟槽中的第一金属层的至少一部分，在第一沟槽的其余部分和第二沟槽的其余部分中形成第二金属层，回流第二金属层，以及 进行化学机械抛光（CMP）。

公开(公告)号：US07824990B2

公开(公告)日：2010-11-02

申请号：US11328933

申请日：2006-01-10

Applicant: Vincent S. Chang ,  Fong-Yu Yen ,  Peng-Soon Lim ,  Jin Ying ,  Hun-Jan Tao

Inventor： Vincent S. Chang ,  Fong-Yu Yen ,  Peng-Soon Lim ,  Jin Ying ,  Hun-Jan Tao

IPC: H01L21/336 ,  H01L21/31

CPC classification number: H01L21/02175 ,  H01L21/0228 ,  H01L21/02337 ,  H01L21/28079 ,  H01L21/28194 ,  H01L21/3141 ,  H01L21/31645 ,  H01L29/1054 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor structure having a high-k dielectric and its method of manufacture is provided. A method includes forming a first dielectric layer over the substrate, a metal layer over the first dielectric layer, and a second dielectric layer over the metal layer. A method further includes annealing the substrate in an oxidizing ambient until the three layers form a homogenous high-k dielectric layer. Forming the first and second dielectric layers comprises a non-plasma deposition process such atomic layer deposition (ALD), or chemical vapor deposition (CVD). A semiconductor device having a high-k dielectric comprises an amorphous high-k dielectric layer, wherein the amorphous high-k dielectric layer comprises a first oxidized metal and a second oxidized metal. The atomic ratios of all oxidized metals are substantially uniformly within the amorphous high-k dielectric layer.

Abstract translation: 提供具有高k电介质的半导体结构及其制造方法。 一种方法包括在衬底上形成第一介电层，在第一介电层上形成金属层，在金属层上方形成第二电介质层。 一种方法还包括在氧化环境中退火衬底，直到三层形成均匀的高k电介质层。 形成第一和第二电介质层包括诸如原子层沉积（ALD）或化学气相沉积（CVD）的非等离子体沉积工艺。 具有高k电介质的半导体器件包括非晶高k电介质层，其中非晶高k电介质层包括第一氧化金属和第二氧化金属。 所有氧化金属的原子比在非晶高k电介质层内基本均匀。