公开(公告)号：US08830750B1

公开(公告)日：2014-09-09

申请号：US13928356

申请日：2013-06-26

Applicant: Phison Electronics Corp.

Inventor： Kuo-Yi Cheng ,  Wei Lin ,  Yu-Hsiang Lin ,  Shao-Wei Yen ,  Kuo-Hsin Lai

IPC: G11C16/06 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5621

Abstract: A data reading method for a rewritable non-volatile memory module is provided. The method includes determining a corresponding read voltage based on a critical voltage distribution of memory cells of a word line. The method further includes: if the critical voltage distribution of the memory cells is a right-offset distribution, applying a set of right adjustment read voltage to the word line to read a plurality of bit data as corresponding soft values; and decoding the corresponding soft values to obtain page data stored in the memory cells. Herein, the set of right adjustment read voltage includes a plurality of positive adjustment read voltages and a plurality of negative adjustment read voltages and the number of the positive adjustment read voltages is more than the number of the negative adjustment read voltages. Accordingly, storage states of the memory cells can be identified correctly.

Abstract translation: 提供了一种可重写非易失性存储器模块的数据读取方法。 该方法包括基于字线的存储器单元的临界电压分布来确定相应的读取电压。 该方法还包括：如果存储器单元的临界电压分布是右偏移分布，则将一组正确的调整读取电压施加到字线以读取多个位数据作为相应的软值; 并解码对应的软值以获得存储在存储单元中的页面数据。 这里，正确调整读取电压的集合包括多个正调整读取电压和多个负调整读取电压，并且正调整读取电压的数量大于负调整读取电压的数量。 因此，可以正确地识别存储器单元的存储状态。

公开(公告)号：US20230289102A1

公开(公告)日：2023-09-14

申请号：US17724504

申请日：2022-04-20

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Hsiang Lin ,  Bo Lun Huang

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: An encoding control method, a memory storage device and a memory control circuit unit are disclosed. The method includes: performing, by an encoding circuit, a first encoding operation to generate first parity data according to write data, a first sub-matrix and a second sub-matrix of a parity check matrix; performing, by the encoding circuit, a second encoding operation to generate second parity data according to the write data, the first parity data, a third sub-matrix, a fourth sub-matrix and a fifth sub-matrix of the parity check matrix; and sending a first write command sequence to instruct a storing of the write data, the first parity data and the second parity data to a rewritable non-volatile memory module.

公开(公告)号：US11430538B1

公开(公告)日：2022-08-30

申请号：US17195547

申请日：2021-03-08

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Hsiang Lin ,  Pochiao Chou ,  Cheng-Che Yang

IPC: G11C29/42 ,  G11C29/18 ,  G11C29/44

Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The method includes: executing a single page encoding operation on first data stored in a first type physical unit to generate local parity data; executing a global encoding operation on second data stored in at least two of the first type physical unit, a second type physical unit, and a third type physical unit to generate global parity data; reading the second data from the at least two of the first type physical unit, the second type physical unit, and the third type physical unit in response to a failure of a single page decoding operation for the first data; and executing a global decoding operation on the second data according to the global parity data.

公开(公告)号：US10522234B2

公开(公告)日：2019-12-31

申请号：US15890326

申请日：2018-02-06

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Hsiang Lin ,  Yu-Cheng Hsu

IPC: G11C29/00 ,  G11C16/34 ,  G06F11/10 ,  G11C16/10 ,  G11C29/52 ,  G11C16/26

Abstract: A bit tagging method, a memory control circuit unit and a memory storage device are provided. The method includes: reading first memory cells according to a first reading voltage to generate a first codeword and determining whether the first codeword is a valid codeword, and the first codeword includes X bits; if not, reading the first memory cells according to a second reading voltage to generate a second codeword and determining whether the second codeword is the valid codeword, and the second codeword includes X bits; and if the second codeword is not the valid codeword and a Yth bit in the X bits of the first codeword is different from a Yth bit in the X bits of the second codeword, recording the Yth bit in the X bits as an unreliable bit, and Y is a positive integer less than or equal to X.

公开(公告)号：US20190189228A1

公开(公告)日：2019-06-20

申请号：US15890326

申请日：2018-02-06

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Hsiang Lin ,  Yu-Cheng Hsu

IPC: G11C16/34 ,  G06F11/10 ,  G11C29/52 ,  G11C16/26 ,  G11C16/10

Abstract: A bit tagging method, a memory control circuit unit and a memory storage device are provided. The method includes: reading first memory cells according to a first reading voltage to generate a first codeword and determining whether the first codeword is a valid codeword, and the first codeword includes X bits; if not, reading the first memory cells according to a second reading voltage to generate a second codeword and determining whether the second codeword is the valid codeword, and the second codeword includes X bits; and if the second codeword is not the valid codeword and a Yth bit in the X bits of the first codeword is different from a Yth bit in the X bits of the second codeword, recording the Yth bit in the X bits as an unreliable bit, and Y is a positive integer less than or equal to X.

公开(公告)号：US20170302299A1

公开(公告)日：2017-10-19

申请号：US15188995

申请日：2016-06-22

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Hsiang Lin ,  Cheng-Che Yang ,  Shao-Wei Yen ,  Kuo-Hsin Lai

IPC: H03M13/29 ,  G06F11/10 ,  G11C29/52 ,  H03M13/11

CPC classification number: H03M13/2906 ,  G06F11/1012 ,  G06F11/1068 ,  G11C29/52 ,  G11C29/702 ,  H03M13/1102 ,  H03M13/2927 ,  H03M13/3776

Abstract: A data processing method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving first write data; performing a first stage encoding operation of a low-density parity-check (LDPC) code on the first write data and generating first transition data; performing a second stage encoding operation of the LDPC code on the first transition data and generating a first error correcting code (ECC); receiving second write data; and performing the first stage encoding operation of the LDPC code on the second write data during a time period of performing the second stage encoding operation of the LDPC code on the first transition data. Accordingly, the data processing efficiency corresponding to the LDPC code can be improved.

公开(公告)号：US09583217B2

公开(公告)日：2017-02-28

申请号：US14296383

申请日：2014-06-04

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Shao-Wei Yen ,  Yu-Hsiang Lin ,  Kuo-Hsin Lai

IPC: G11C29/00 ,  G11C29/52 ,  H03M13/37 ,  G06F11/10 ,  G11C29/04

CPC classification number: G11C29/52 ,  G06F11/1012 ,  G11C2029/0411 ,  H03M13/05 ,  H03M13/3746

Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided, the decoding method includes: reading a plurality of memory cells according to hard decision voltage to obtain hard bit; performing a parity check procedure for the hard bit to obtain a plurality of syndromes; determining whether the hard bit has error according to the syndromes; if the hard bit has the error, updating the hard bit according to channel information of the hard bit and syndrome weight information corresponding to the hard bit.

Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路单元，该解码方法包括：根据硬判定电压读取多个存储单元以获得硬比特; 对所述硬比特执行奇偶校验处理以获得多个综合征; 根据综合征确定硬比特是否有错误; 如果硬比特错误，则根据与硬比特相对应的硬比特和综合征权重信息的信道信息更新硬比特。

公开(公告)号：US20150186212A1

公开(公告)日：2015-07-02

申请号：US14190103

申请日：2014-02-26

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Shao-Wei Yen ,  Yu-Hsiang Lin ,  Kuo-Hsin Lai

IPC: G06F11/10

CPC classification number: G06F11/1076 ,  G06F11/1012 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5642 ,  G11C2029/0411 ,  H03M13/1102 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/3707

Abstract: A decoding method, a memory storage device and a memory controlling circuit unit are provided. The decoding method includes: reading at least one memory cell according to a first read voltage to obtain at least one first verification bit; executing a hard bit mode decoding procedure according to the first verification bit, and determining whether a first valid codeword is generated by the hard bit mode decoding procedure; if the first valid codeword is not generated by the hard bit mode decoding procedure, obtaining storage information of the memory cell; deciding a voltage number according to the storage information; reading the memory cell according to second read voltages matching the voltage number to obtain second verification bits; and executing a soft bit mode decoding procedure according to the second verification bits. Accordingly, the speed of decoding is increased.

Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路单元。 解码方法包括：根据第一读取电压读取至少一个存储器单元以获得至少一个第一验证位; 执行根据第一验证位的硬比特模式解码过程，以及通过硬比特模式解码过程来确定是否产生第一有效码字; 如果第一有效码字不是由硬比特模式解码过程产生的，则获得存储单元的存储信息; 根据存储信息确定电压数; 根据与电压数相匹配的第二读取电压来读取存储器单元以获得第二验证位; 以及根据第二验证位执行软位模式解码过程。 因此，解码速度提高。

公开(公告)号：US20250068509A1

公开(公告)日：2025-02-27

申请号：US18490762

申请日：2023-10-20

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Hsiang Lin ,  Shih-Jia Zeng

IPC: G06F11/10

Abstract: A decoding method, a memory storage device, and a memory control circuit unit are provided. The decoding method is described below. A read command sequence is transmitted, the read command sequence instructs to read a first physical unit, and the first physical unit belongs to a physical unit group. A first single-frame decoding is performed on a first data frame read from the first physical unit. First error evaluation information corresponding to the physical unit group is obtained in response to the first single-frame decoding being failed and a default condition not being satisfied. This default condition is used for triggering the multi-frame decoding on the physical unit group. A second single-frame decoding is performed on the first data frame according to the first error evaluation information.

公开(公告)号：US11190217B2

公开(公告)日：2021-11-30

申请号：US16788320

申请日：2020-02-12

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Hsiang Lin ,  Shao-Wei Yen ,  Chih-Kang Yeh

IPC: H03M13/29 ,  G06F11/10 ,  H03M13/53

Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: obtaining a data; encoding a plurality of sub-data in the data to obtain a plurality of first error checking and correction codes respectively corresponding to the plurality of sub-data; writing the plurality of sub-data and the plurality of first error checking and correction codes into a first physical programming unit; encoding the plurality of sub-data to obtain a second error checking and correction code; and writing the second error checking and correction code into a second physical programming unit.