知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

17 records (took 0.02 seconds)

    FABRICATING METHOD OF NON-VOLATILE MEMORY DEVICE
    11.
    发明申请
    FABRICATING METHOD OF NON-VOLATILE MEMORY DEVICE 审中-公开
    非易失性存储器件的制造方法

    公开(公告)号：US20150235893A1

    公开(公告)日：2015-08-20

    申请号：US14704986

    申请日：2015-05-06

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Hiroshi Watanabe

    IPC: H01L21/768 ,  H01L27/115

    CPC classification number: H01L21/768 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  H01L23/5222 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L29/788 ,  H01L29/7881

    Abstract: Provided is a fabrication method of a non-volatile memory device having a zigzag body wiring. First word lines and second word lines are formed on a substrate, wherein the first word lines and the second word lines are arranged periodically and extend in a first direction. Bit lines are formed over the first and second word lines, wherein a first distance from the first word lines to the substrate is smaller than a second distance from the second word lines to the substrate.

    Abstract translation: 提供了具有锯齿形主体布线的非易失性存储器件的制造方法。 第一字线和第二字线形成在衬底上，其中第一字线和第二字线周期性地布置并沿第一方向延伸。 位线形成在第一和第二字线之上，其中从第一字线到衬底的第一距离小于从第二字线到衬底的第二距离。

    INTEGRATED CIRCUIT AND CODE GENERATING METHOD
    12.
    发明申请
    INTEGRATED CIRCUIT AND CODE GENERATING METHOD 有权
    集成电路和代码生成方法

    公开(公告)号：US20150091747A1

    公开(公告)日：2015-04-02

    申请号：US14038772

    申请日：2013-09-27

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Hiroshi Watanabe

    IPC: G08C19/28 ,  H01L29/78 ,  H01L27/105

    CPC classification number: H01L29/785 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  H03K3/84

    Abstract: An integrated circuit and a code generating method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.

    Abstract translation: 描述了集成电路和代码生成方法。 集成电路包括多个场效应晶体管，多个读出放大器和处理电路。 每个场效应晶体管被配置为表示映射表中的地址，并且包括源极，漏极，沟道和栅极。 每个读出放大器连接到漏极并被配置为感测来自漏极的电流，并且识别相应的场效应晶体管的阈值电压。 处理电路被配置为将由相应的感测放大器识别的每个阈值电压分类为第一状态和第二状态，并且将映射表中相应地址处的每个阈值电压的状态标记。

    Memory management method, memory storage device and memory controlling circuit unit
    15.
    发明授权
    Memory management method, memory storage device and memory controlling circuit unit 有权
    存储器管理方法，存储器存储器件和存储器控制电路单元

    公开(公告)号：US09224492B1

    公开(公告)日：2015-12-29

    申请号：US14623510

    申请日：2015-02-17

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Hiroshi Watanabe

    IPC: G11C29/04 ,  G11C29/14 ,  G11C29/44 ,  G11C29/50 ,  G11C16/34 ,  G11C16/26 ,  G11C29/00

    CPC classification number: G11C16/34 ,  G11C11/5642 ,  G11C16/26 ,  G11C29/00 ,  G11C29/028 ,  G11C29/14 ,  G11C29/4401 ,  G11C29/50004

    Abstract: An memory management method, a memory storage device and a memory controlling circuit unit are provided. The method comprises: obtaining a threshold voltage distribution of memory cells, wherein the threshold voltage distribution comprises a plurality of states, and each of the states represents a storage status; determining whether a width of a gap window between two neighboring states among the states is less than a threshold value; and if the width of the gap window is less than the threshold value, eliminating one of the two neighboring states.

    Abstract translation: 提供存储器管理方法，存储器存储装置和存储器控制电路单元。 该方法包括：获得存储器单元的阈值电压分布，其中阈值电压分布包括多个状态，并且每个状态表示存储状态; 确定所述状态中两个相邻状态之间的间隙窗口的宽度是否小于阈值; 并且如果间隙窗口的宽度小于阈值，则消除两个相邻状态之一。

    Non-volatile memory device and operation and fabricating methods thereof
    16.
    发明授权
    Non-volatile memory device and operation and fabricating methods thereof 有权
    非易失性存储器件及其操作和制造方法

    公开(公告)号：US09064968B2

    公开(公告)日：2015-06-23

    申请号：US13969626

    申请日：2013-08-19

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Hiroshi Watanabe

    IPC: G11C16/16 ,  H01L29/788 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  H01L21/768 ,  G11C16/10

    CPC classification number: H01L21/768 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  H01L23/5222 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L29/788 ,  H01L29/7881

    Abstract: Provided is a non-volatile memory device having a zigzag body wiring. First word lines and second word lines are disposed on a substrate, arranged periodically and extended along a first direction. First inter-poly dielectric films are disposed on the substrate and respectively beneath the first word lines. Second inter-poly dielectric films are disposed on the substrate and respectively beneath the second word lines, wherein the first inter-poly dielectric films are thinner than the second inter-poly dielectric films. A floating gate is disposed between the substrate and each of the first and second inter-poly dielectric films. A tunnel oxide film is disposed between the substrate and each of the floating gates. Bit lines are disposed above the first and second word lines and extended along a second direction different from the first direction.

    Abstract translation: 提供了具有锯齿形主体布线的非易失性存储器件。 第一字线和第二字线被布置在基板上，周期性地布置并沿着第一方向延伸。 第一多晶硅介电膜设置在基板上并分别在第一字线下方。 第二多晶硅介电膜设置在基板上并分别在第二字线的下方，其中第一多晶硅介电膜比第二多晶硅介电膜薄。 浮置栅极设置在基板和第一和第二多晶硅间绝缘膜中的每一个之间。 隧道氧化膜设置在衬底和每个浮动栅极之间。 位线设置在第一和第二字线上方并沿着不同于第一方向的第二方向延伸。

    INTEGRATED CIRCUIT, CODE GENERATING METHOD, AND DATA EXCHANGE METHOD
    17.
    发明申请
    INTEGRATED CIRCUIT, CODE GENERATING METHOD, AND DATA EXCHANGE METHOD 有权
    集成电路，代码生成方法和数据交换方法

    公开(公告)号：US20150092777A1

    公开(公告)日：2015-04-02

    申请号：US14335957

    申请日：2014-07-21

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Hiroshi Watanabe

    IPC: H04L29/06 ,  H04L12/741 ,  H03K3/36 ,  H01L27/105 ,  H01L29/78

    CPC classification number: H04L63/0876 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H03K3/36 ,  H03K3/84 ,  H04L9/3278 ,  H04L45/745 ,  H04L63/061

    Abstract: An integrated circuit, a code generating method, and a data exchange method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.

    Abstract translation: 描述了集成电路，代码生成方法和数据交换方法。 集成电路包括多个场效应晶体管，多个读出放大器和处理电路。 每个场效应晶体管被配置为表示映射表中的地址，并且包括源极，漏极，沟道和栅极。 每个读出放大器连接到漏极并被配置为感测来自漏极的电流，并且识别相应的场效应晶体管的阈值电压。 处理电路被配置为将由相应的感测放大器识别的每个阈值电压分类为第一状态和第二状态，并且将映射表中相应地址处的每个阈值电压的状态标记。

Patent Agency Ranking