公开(公告)号：US09806918B1

公开(公告)日：2017-10-31

申请号：US15181167

申请日：2016-06-13

Applicant: Oracle International Corporation

Inventor： Jianghui Su ,  Rajesh Kumar ,  Ranjan Vaish

IPC: H04L25/03 ,  H04L25/02 ,  H04B1/16

CPC classification number: H04L25/03146 ,  H04L25/028 ,  H04L25/03343

Abstract: Embodiments include systems and methods for providing fast direct feedback to correct decision feedback equalization (DFE) in receiver circuits. Embodiments can provide direct feedback for DFE correction in a manner that is effective in high-speed data channels, while manifesting less latency, power consumption, and/or area than conventional DFE implementations. In some implementations, in each clock cycle (e.g., Tn), implementations can select (e.g., using a multiplexer) between a positive reference signal and a negative reference signal (e.g., both reference signals generated according to an inter-symbol interference magnitude for a data channel) according to a decision feedback signal from a previous clock cycle (Tn−1). The selected reference signal can be compared (e.g., in the same clock cycle Tn, using a comparator) with an input data signal to generated an updated decision feedback signal for a next clock cycle (e.g., Tn+1).

公开(公告)号：US20160301435A1

公开(公告)日：2016-10-13

申请号：US14681796

申请日：2015-04-08

Applicant: Oracle International Corporation

Inventor： Jianghui Su ,  Yan Yan ,  Jieda Li

IPC: H04B1/10 ,  H04B17/21 ,  H04B17/24

CPC classification number: H04L25/08 ,  H04B17/21 ,  H04B17/24 ,  H04L25/03114 ,  H04L25/06 ,  H04L25/14

Abstract: An embodiment includes a receiver circuit, a feedback circuit and a control circuit. The receiver circuit is configured to receive each data bit of a plurality of data bits. The feedback circuit is configured to measure a first interference level generated by a first data bit of a first subset of the plurality of data bits on a second data bit of the plurality of data bits to generate one of a first plurality of feedback values. The feedback circuit is also configured to measure a second interference level generated by a third data bit of a second subset of the plurality of data bits on a fourth data bit of the plurality of data bits to generate one of a second plurality of feedback values. The control circuit is configured to determine a duty cycle dependent upon a comparison of the first plurality to the second plurality.

Abstract translation: 实施例包括接收器电路，反馈电路和控制电路。 接收器电路被配置为接收多个数据位的每个数据位。 反馈电路被配置为测量由多个数据位的第二数据位上的多个数据位的第一子集的第一数据位产生的第一干扰电平，以产生第一多个反馈值之一。 反馈电路还被配置为测量由多个数据位的第四数据位上的多个数据位的第二子集的第三数据位产生的第二干扰电平，以产生第二多个反馈值之一。 控制电路被配置为确定取决于第一多个到第二个的比较的占空比。

公开(公告)号：US09306732B2

公开(公告)日：2016-04-05

申请号：US14146605

申请日：2014-01-02

Applicant: Oracle International Corporation

Inventor： Dawei Huang ,  Jianghui Su ,  Hongtao Zhang ,  Deqiang Song

IPC: H04L7/00 ,  H04L7/02 ,  H04L7/033

CPC classification number: H04L7/0087 ,  H04L7/02 ,  H04L7/0334

Abstract: Embodiments include systems and methods for applying a controllable early/late offset to an at-rate clock data recovery (CDR) system. Some embodiments operate in context of a CDR circuit of a serializer/deserializer (SERDES). For example, slope asymmetry around the first precursor of the channel pulse response for the SERDES can tend to skew at-rate CDR determinations of whether to advance or retard clocking. Accordingly, embodiments use asymmetric voting thresholds for generating each of the advance and retard signals in an attempt to de-skew the voting results and effectively tune the CDR to a position either earlier or later than the first precursor zero crossing (i.e., h(−1)=0) position. This can improve link margin and data recovery, particularly for long data channels and/or at higher data rates.

Abstract translation: 实施例包括将可控早/迟补偿应用于速率时钟数据恢复（CDR）系统的系统和方法。 一些实施例在串行器/解串器（SERDES）的CDR电路的上下文中操作。 例如，针对SERDES的信道脉冲响应的第一前体周围的斜率不对称倾向于偏移速率CDR确定是否提前或延迟时钟。 因此，实施例使用非对称投票阈值来产生提前和延迟信号中的每一个，以试图使投票结果去偏移，并有效地将CDR调谐到比第一前体过零点更早或更晚的位置（即h（ - 1）= 0）位置。 这可以改善链路余量和数据恢复，特别是对于长数据信道和/或更高的数据速率。

公开(公告)号：US09052900B2

公开(公告)日：2015-06-09

申请号：US13753130

申请日：2013-01-29

Applicant: Oracle International Corporation

Inventor： Hongtao Zhang ,  Da-wei Huang ,  Jianghui Su

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  H04L12/6418

Abstract: Systems and methods for reducing power consumption of systems using serialized data transmission. In a multi-node system, the reiterative steps for the setup of the lanes within links between the nodes produces both a time invariant set of parameters associated with the channel properties of the lanes and a time variant set of parameters associated with receiver clock alignment. The time invariant set is stored in persistent storage. Links may be turned on and turned off. When a link is turned on again, the stored time invariant set may be used as initial values to reconfigure both the time invariant and the time variant sets, thereby greatly reducing the delay to begin using the link again. The reduced delay may significantly speed up the wakening process for the links, thereby encouraging the use of low-power techniques that include tuning off lanes.

Abstract translation: 使用串行数据传输降低系统功耗的系统和方法。 在多节点系统中，用于在节点之间的链路内建立通道的重复步骤产生与通道的通道属性相关联的时间不变量参数和与接收器时钟对准相关联的参数的时变集合。 时间不变集存储在持久存储器中。 链接可能会打开并关闭。 当再次打开链接时，可以将所存储的时间不变集合用作初始值以重新配置时间不变集合和时间变量集合，从而大大减少开始再次使用链接的延迟。 减少的延迟可能会显着加速链路的唤醒过程，从而鼓励使用包括调整车道的低功率技术。

公开(公告)号：US11784855B2

公开(公告)日：2023-10-10

申请号：US18154248

申请日：2023-01-13

Applicant: Oracle International Corporation

Inventor： Xun Zhang ,  Chaitanya Palusa ,  Dawei Huang ,  Muthukumar Vairavan ,  Jianghui Su

IPC: H04L25/03 ,  H04B1/16

CPC classification number: H04L25/03057 ,  H04B1/16

Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, the equalized input signal to generate multiple samples of a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.

公开(公告)号：US20220191071A1

公开(公告)日：2022-06-16

申请号：US17648899

申请日：2022-01-25

Applicant: Oracle International Corporation

Inventor： Xun Zhang ,  Chaitanya Palusa ,  Dawei Huang ,  Muthukumar Vairavan ,  Jianghui Su

IPC: H04L25/03 ,  H04B1/16

Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, the equalized input signal to generate multiple samples of a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.

公开(公告)号：US10142134B2

公开(公告)日：2018-11-27

申请号：US15456778

申请日：2017-03-13

Applicant: Oracle International Corporation

Inventor： Jiangyuan Li ,  Xun Zhang ,  Jianghui Su

IPC: H04L12/825 ,  H04L25/03

Abstract: Embodiments include systems and methods for implementing a multi-rate FIR by using rate-dependent bit stuffing on the cursor, while using rate-independent (e.g., full-rate) spacing on the pre- and post-cursor. For example, in the FIR data path, the cursor bit output is generated using bit stuffing, depending on a selected rate mode (e.g., full-rate, half-rate, quarter-rate, eighth-rate, etc.), but the spacing of the pre-cursor, cursor, and post-cursor are maintained at 1 UI apart (i.e., the full-rate spacing) for all rate modes. Such an approach can appreciably reduce complexity of the logic and can appreciably relieve the critical timing path.

公开(公告)号：US09484967B1

公开(公告)日：2016-11-01

申请号：US14681796

申请日：2015-04-08

Applicant: Oracle International Corporation

Inventor： Jianghui Su ,  Yan Yan ,  Jieda Li

IPC: H04L25/08 ,  H04B1/10 ,  H04B17/24 ,  H04B17/21

CPC classification number: H04L25/08 ,  H04B17/21 ,  H04B17/24 ,  H04L25/03114 ,  H04L25/06 ,  H04L25/14

Abstract: An embodiment includes a receiver circuit, a feedback circuit and a control circuit. The receiver circuit is configured to receive each data bit of a plurality of data bits. The feedback circuit is configured to measure a first interference level generated by a first data bit of a first subset of the plurality of data bits on a second data bit of the plurality of data bits to generate one of a first plurality of feedback values. The feedback circuit is also configured to measure a second interference level generated by a third data bit of a second subset of the plurality of data bits on a fourth data bit of the plurality of data bits to generate one of a second plurality of feedback values. The control circuit is configured to determine a duty cycle dependent upon a comparison of the first plurality to the second plurality.

Abstract translation: 实施例包括接收器电路，反馈电路和控制电路。 接收器电路被配置为接收多个数据位的每个数据位。 反馈电路被配置为测量由多个数据位的第二数据位上的多个数据位的第一子集的第一数据位产生的第一干扰电平，以产生第一多个反馈值之一。 反馈电路还被配置为测量由多个数据位的第四数据位上的多个数据位的第二子集的第三数据位产生的第二干扰电平，以产生第二多个反馈值之一。 控制电路被配置为确定取决于第一多个到第二个的比较的占空比。

公开(公告)号：US09141459B2

公开(公告)日：2015-09-22

申请号：US14146904

申请日：2014-01-03

Applicant: Oracle International Corporation

Inventor： Jianghui Su ,  Pu Chuang ,  Yan Yan

IPC: G06F11/00 ,  G06F11/07

CPC classification number: H04L1/205

Abstract: A system may include one or more high-speed serial interfaces for moving data. A system may include a transmission unit configured to serially transmit data bits, and a receiving unit coupled to the transmission unit. The receiving unit may receive a stream of data bits from the transmission unit and establish an initial sample point. The receiving unit may then sample the bits at multiple offsets from the initial sample point, reestablishing the initial sample point between each offset. The receiving unit may also calculate bit error rates (BERs) for the samples taken at each sample point. Based on the BERs, the receiving unit may set a data sampling point for receiving a second stream of data bits from the transmitter unit. The receiving unit may limit the amount of time the data sampling point is used and recalculate the data sampling point when the amount of time has expired.

Abstract translation: 系统可以包括用于移动数据的一个或多个高速串行接口。 系统可以包括被配置为串行发送数据位的传输单元和耦合到传输单元的接收单元。 接收单元可以从传输单元接收数据比特流并建立初始采样点。 然后，接收单元可以从初始采样点以多个偏移采样位，重新建立每个偏移之间的初始采样点。 接收单元还可以计算在每个采样点采集的采样的误码率（BER）。 基于BER，接收单元可以设置用于从发送器单元接收第二数据比特流的数据采样点。 接收单元可以限制使用数据采样点的时间量，并且在时间量过期时重新计算数据采样点。

公开(公告)号：US09036757B1

公开(公告)日：2015-05-19

申请号：US14493652

申请日：2014-09-23

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Jianghui Su ,  Francis Schumacher ,  Zuxu Qin ,  Dawei Huang

IPC: H04L7/00

CPC classification number: H04L7/10 ,  H04L7/0062

Abstract: Embodiments include systems and methods for applying post-cursor locking point adjustment to an at-rate clock data recovery (CDR) system. Some embodiments operate in context of a CDR circuit of a serializer/deserializer (SERDES). In one embodiment, a training routine is used to determine an optimal post-cursor target level. Increasing or decreasing the post-cursor target level can cause the CDR clocking to shift right or left, which can be seen as a shift of the channel impulse response with respect to the CDR sampling locations. In some implementations, the post-cursor can be locked to the determined target level. In other implementations, the determined target level can be compared to a fully-adapted post-cursor to tune adaptations performed by transmitter and/or receiver equalizers.

Abstract translation: 实施例包括用于将速度锁定点调整应用于速率时钟数据恢复（CDR）系统的系统和方法。 一些实施例在串行器/解串器（SERDES）的CDR电路的上下文中操作。 在一个实施例中，使用训练例程来确定最佳的后视标目标水平。 增加或减少后视标目标水平可能导致CDR时钟向右或向左移动，这可以被看作是信道脉冲响应相对于CDR采样位置的移位。 在一些实现中，后视标可以被锁定到确定的目标级别。 在其他实施方式中，可以将确定的目标水平与完全适配的后置光标进行比较，以调谐由发射机和/或接收机均衡器执行的适配。