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    Method for preparing recessed gate structure with protection layer
    11.
    发明授权
    Method for preparing recessed gate structure with protection layer 有权

    公开(公告)号：US12211905B2

    公开(公告)日：2025-01-28

    申请号：US17672138

    申请日：2022-02-15

    Applicant: NANYA TECHNOLOGY CORPORATION

    Inventor： Kuo-Hui Su

    IPC: H01L29/40 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L29/423 ,  H01L29/51

    Abstract: A method for preparing a recessed gate structure includes forming a recessed structure, wherein the recessed structure comprises a substrate with the recess extending into the substrate from a topmost surface of the substrate; forming a first functional layer to at least cover a sidewall of a recess of the recessed structure; forming a second functional layer to cover the first functional layer; performing a rapid thermal treatment to form an interfacial layer extending along an interface between the first functional layer and the second functional layer; and forming a conductive feature to fill up the recess.

    Semiconductor device with nanowire plugs and method for fabricating the same
    13.
    发明授权
    Semiconductor device with nanowire plugs and method for fabricating the same 有权

    公开(公告)号：US11107809B2

    公开(公告)日：2021-08-31

    申请号：US16582248

    申请日：2019-09-25

    Applicant: NANYA TECHNOLOGY CORPORATION

    Inventor： Kuo-Hui Su

    IPC: H01L27/08 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L21/48 ,  H01L23/64

    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having first regions and second regions; a plurality of bit line contacts and a plurality of capacitor contacts disposed over the plurality of first regions and second regions; a landing pad disposed over one of the plurality of capacitor contacts, the landing pad comprising a protruding portion of a capacitor plug and a first spacer disposed on a sidewall of the protruding portion; a conductive plug disposed over the landing pad; and a plurality of bit lines disposed over the plurality of bit line contacts; and a capacitor structure disposed over the conductive plug. The capacitor plug includes a plurality of nanowires, a conductive liner disposed over the plurality of nanowires, and a conductor disposed over the conductive liner.

    Semiconductor package and method for preparing the same
    14.
    发明授权
    Semiconductor package and method for preparing the same 有权

    公开(公告)号：US10985151B2

    公开(公告)日：2021-04-20

    申请号：US16389167

    申请日：2019-04-19

    Applicant: NANYA TECHNOLOGY CORPORATION

    Inventor： Kuo-Hui Su

    IPC: H01L25/18 ,  H01L23/31 ,  H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/522 ,  H01L21/768

    Abstract: The present disclosure relates to a semiconductor package and a method for preparing the same. The semiconductor package includes a lower semiconductor layer, an upper semiconductor layer, a fixturing structure, and a molding layer. The lower semiconductor layer includes an attached region and a fixturing region adjacent to the attached region. The upper semiconductor layer is disposed over the attached region. The fixturing structure is disposed adjacent to the upper semiconductor layer. The fixturing structure has at least one fixturing hole, the fixturing hole has an opening corresponding to the fixturing region, and the opening has a first width. The molding layer covers side walls of the upper semiconductor layer. The molding layer has at least one fixturing protrusion extending into the fixturing hole, the fixturing protrusion has a first expanding portion below the opening, and the first expanding portion has a second width greater than the first width.

    Semiconductor memory device with air gaps for reducing capacitive coupling and method for preparing the same
    17.
    发明授权
    Semiconductor memory device with air gaps for reducing capacitive coupling and method for preparing the same 有权

    公开(公告)号：US11444087B2

    公开(公告)日：2022-09-13

    申请号：US16857890

    申请日：2020-04-24

    Applicant: NANYA TECHNOLOGY CORPORATION

    Inventor： Kuo-Hui Su

    IPC: H01L27/108 ,  H01L23/532 ,  H01L21/768

    Abstract: The present disclosure provides a semiconductor memory device with air gaps for reducing capacitive coupling between a bit line and an adjacent conductive feature and a method for preparing the semiconductor memory device. The semiconductor memory device includes a substrate; an isolation member defining an active region having a first P-type ion concentration in the substrate; a gate structure disposed in the substrate; a first doped region positioned at a first side of the gate structure in the active region; a second doped region positioned at a second side of the gate structure in the active region; a bit line positioned on the first doped region; an air gap positioned adjacent to the bit line; a capacitor plug disposed on the second doped region and a barrier layer on a sidewall of the capacitor plug; and a landing pad on a top portion of the capacitor plug, wherein the landing pad comprises a first silicide layer disposed over a protruding portion of the capacitor plug, and a second silicide layer disposed on a sidewall of the barrier layer.

    Method for preparing semiconductor device with air gap structure
    18.
    发明授权
    Method for preparing semiconductor device with air gap structure 有权

    公开(公告)号：US11417667B2

    公开(公告)日：2022-08-16

    申请号：US17130478

    申请日：2020-12-22

    Applicant: NANYA TECHNOLOGY CORPORATION

    Inventor： Kuo-Hui Su

    IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L27/108 ,  H01L23/528 ,  H01L23/522 ,  H01L29/06

    Abstract: The present application discloses a method for preparing a semiconductor device with an air gap structure between conductive structures. The method includes: forming a first bit line, a second bit line, a first capacitor contact and a second capacitor contact over a semiconductor substrate, wherein the first capacitor contact and the second capacitor contact are disposed between the first bit line and the second bit line; forming a first dielectric layer over a sidewall of the first bit line, a sidewall of the second bit line, a sidewall of the first capacitor contact and a sidewall of the second capacitor contact such that an opening is formed and surrounded by the first dielectric layer; filling the opening with a dielectric structure; and removing the first dielectric layer to form an opening structure surrounding the dielectric structure.

    Semiconductor device with reduced critical dimensions and method of manufacturing the same
    19.
    发明授权
    Semiconductor device with reduced critical dimensions and method of manufacturing the same 有权

    公开(公告)号：US11355342B2

    公开(公告)日：2022-06-07

    申请号：US16440354

    申请日：2019-06-13

    Applicant: NANYA TECHNOLOGY CORPORATION

    Inventor： Kuo-Hui Su

    IPC: H01L21/3115 ,  H01L21/033 ,  H01L21/02

    Abstract: A semiconductor structure includes a base layer with a top surface and a plurality of processed areas. A primary pattern is disposed on the top surface of the base layer, wherein the primary pattern has a pattern top surface, a processed area on the pattern top surface, and a sidewall, and the primary pattern has a first critical dimension, and the processed areas are on the part of the top surface of the base layer exposed by the primary pattern. A secondary pattern is disposed on the sidewall of the primary pattern, wherein the secondary pattern has a second critical dimension, and the second critical dimension is smaller than the first critical dimension.

    Semiconductor device and manufacturing method thereof
    20.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US10651157B1

    公开(公告)日：2020-05-12

    申请号：US16283081

    申请日：2019-02-22

    Applicant: NANYA TECHNOLOGY CORPORATION

    Inventor： Kuo-Hui Su

    IPC: H01L25/065 ,  H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L25/00

    Abstract: A semiconductor device includes a first substrate, a through substrate via, a second substrate, and a bonding structure. The first substrate includes a first dielectric material, and the first dielectric material includes a first conductive pad embedded therein. The through substrate via is formed in the first substrate. The second substrate includes a second dielectric material, the second dielectric material includes a second conductive pad embedded therein, the first dielectric material is different from the second dielectric material, the second conductive pad has a first height, the second dielectric material has a second height, and the first height is less than the second height. The bonding structure is formed between the first substrate and the second substrate, wherein the bonding structure includes the first conductive pad bonded to the second conductive pad and the first dielectric material bonded to the second dielectric material.

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