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    Transistor And Methods Of Forming Transistors
    13.
    发明申请
    Transistor And Methods Of Forming Transistors 有权

    公开(公告)号：US20210043768A1

    公开(公告)日：2021-02-11

    申请号：US16536479

    申请日：2019-08-09

    Applicant: Micron Technology, Inc.

    Inventor： Manuj Nahar ,  Vassil N. Antonov ,  Darwin Franseda Fan ,  Ali Moballegh

    IPC: H01L29/78 ,  H01L27/108 ,  H01L29/04 ,  H01L21/02 ,  H01L29/66

    Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. An upper material is directly above a lower material. The upper material is in at least one of the top source/drain region, the bottom source/drain region, and the channel region. The lower material is in at least one of the top source/drain region, the bottom source/drain region, and the channel region. The upper material comprises 1 atomic percent to 10 atomic percent elemental-form H and 0 total atomic percent to less than 0.1 total atomic percent of one or more noble elements. The lower material comprises 0 atomic percent to less than 1 atomic percent elemental-form H and 0.1 total atomic percent to 10 total atomic percent of one or more noble elements. Other embodiments, including method, are disclosed.

    Multi-material structures and capacitor-containing semiconductor constructions
    16.
    发明授权
    Multi-material structures and capacitor-containing semiconductor constructions 有权
    多材料结构和含电容器的半导体结构

    公开(公告)号：US09236427B2

    公开(公告)日：2016-01-12

    申请号：US14501423

    申请日：2014-09-30

    Applicant: Micron Technology, Inc.

    Inventor： Joseph Neil Greeley ,  Duane M. Goodner ,  Vishwanath Bhat ,  Vassil N. Antonov ,  Prashant Raghu

    IPC: H01L27/108 ,  H01L29/94 ,  H01L49/02 ,  B82Y30/00

    CPC classification number: H01L28/75 ,  B82Y30/00 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/65 ,  H01L28/90 ,  Y10S977/932 ,  Y10T428/265

    Abstract: Some embodiments include a method of forming a capacitor. An opening is formed through a silicon-containing mass to a base, and sidewalls of the opening are lined with protective material. A first capacitor electrode is formed within the opening and has sidewalls along the protective material. At least some of the silicon-containing mass is removed with an etch. The protective material protects the first capacitor electrode from being removed by the etch. A second capacitor electrode is formed along the sidewalls of the first capacitor electrode, and is spaced from the first capacitor electrode by capacitor dielectric. Some embodiments include multi-material structures having one or more of aluminum nitride, molybdenum nitride, niobium nitride, niobium oxide, silicon dioxide, tantalum nitride and tantalum oxide. Some embodiments include semiconductor constructions.

    Abstract translation: 一些实施例包括形成电容器的方法。 通过含硅物质向基底形成开口，并且开口的侧壁衬有保护材料。 第一电容器电极形成在开口内并具有保护材料的侧壁。 用蚀刻去除至少一些含硅物质。 保护材料保护第一电容器电极不被蚀刻除去。 沿着第一电容器电极的侧壁形成第二电容器电极，并且通过电容器电介质与第一电容器电极间隔开。 一些实施例包括具有氮化铝，氮化钼，氮化铌，氧化铌，二氧化硅，氮化钽和氧化钽中的一种或多种的多材料结构。 一些实施例包括半导体结构。

    Transistor and methods of forming transistors
    20.
    发明授权
    Transistor and methods of forming transistors 有权

    公开(公告)号：US10923593B1

    公开(公告)日：2021-02-16

    申请号：US16536479

    申请日：2019-08-09

    Applicant: Micron Technology, Inc.

    Inventor： Manuj Nahar ,  Vassil N. Antonov ,  Darwin Franseda Fan ,  Ali Moballegh

    IPC: H01L29/78 ,  H01L27/108 ,  H01L29/66 ,  H01L21/02 ,  H01L29/04

    Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. An upper material is directly above a lower material. The upper material is in at least one of the top source/drain region, the bottom source/drain region, and the channel region. The lower material is in at least one of the top source/drain region, the bottom source/drain region, and the channel region. The upper material comprises 1 atomic percent to 10 atomic percent elemental-form H and 0 total atomic percent to less than 0.1 total atomic percent of one or more noble elements. The lower material comprises 0 atomic percent to less than 1 atomic percent elemental-form H and 0.1 total atomic percent to 10 total atomic percent of one or more noble elements. Other embodiments, including method, are disclosed.

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