- Patent Title: Vertical transistors having at least 50% grain boundaries offset between top and bottom source/drain regions and the channel region that is vertically therebetween
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Application No.: US17860325Application Date: 2022-07-08
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Publication No.: US12191354B2Publication Date: 2025-01-07
- Inventor: Manuj Nahar , Vassil N. Antonov , Kamal M. Karda , Michael Mutch , Hung-Wei Liu , Jeffery B. Hull
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L29/08
- IPC: H01L29/08 ; H01L21/02 ; H01L29/04 ; H01L29/06 ; H01L29/66 ; H01L29/78

Abstract:
A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The channel region is crystalline and comprises a plurality of vertically-elongated crystal grains that individually are directly against both of the top source/drain region and the bottom source/drain region. Other embodiments, including methods, are disclosed.
Public/Granted literature
- US20220344468A1 Transistor And Methods Of Forming Transistors Public/Granted day:2022-10-27
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